Datasheet

1082
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
PMECC:
Section 28.2 ”Embedded Characteristics”, added a line on supporting 8-bit Nand Flash data bus.
Section 28.6.11 ”PMECC Interrupt Status Register”, fixed a typo in the register table:
- replaced duplicate bits 31 - 24 by missing 7 - 0
8403
SMC:
Replaced ‘turned out’ with ‘switched to output mode ‘ in Section 30.9.4.1 ”Write is Controlled by NWE
(WRITE_MODE = 1)” and Section 30.9.4.2 ”Write is Controlled by NCS (WRITE_MODE = 0)”.
7925
DDRSDRC:
Replaced TCSR with TCR when related to Section 31.7.7 ”DDRSDRC Low-power Register” to prevent
confusion between JEDEC naming TCSR and the associated bitfield TCR.
Replaced binary configuration values with decimal values throughout the document.
Section 31.7 ”DDR SDR SDRAM Controller (DDRSDRC) User Interface”:
- Table 31-16 ”Register Mapping”, updated offset values for reserved registers (0x54-0xE0, 0xEC-0xFC)
- Section 31.7.3 ”DDRSDRC Configuration Register”:
- DIC: updated the bitfield name from DIC/DIS to DIC and revised the description content
- Section 31.7.11 ”DDRSDRC Write Protect Mode Register”:
- WPKEY: replaced the bitfield description with a table
- described with a table and/or updated data presentation in:
- Section 31.7.1 ”DDRSDRC Mode Register” (MODE)
- Section 31.7.3 ”DDRSDRC Configuration Register” (NC, NR, OCD, NB, DECOD)
- Section 31.7.4 ”DDRSDRC Timing Parameter 0 Register” (TWTR)
- Section 31.7.7 ”DDRSDRC Low-power Register”(LPCB, TIMEOUT, APDE, UPD_MR)
- Section 31.7.8 ”DDRSDRC Memory Device Register” (MD, DBW)
8592
rfo
8968
8592
8883
8883
DMAC:
Added Section 32.3 ”DMA Controller Peripheral Connections” and moved Table 32-1 ”DMA Channel
Definition” from Section 32.2 ”Embedded Characteristics” to this new section.
Section 32.8.1 ”DMAC Global Configuration Register”:
- KEY: replaced the bitfield description with a table
Section 32.8.15 ”DMAC Channel x [x = 0..7] Descriptor Address Register”:
- DSCR_IF bitfield description table: added DMA Master Interface references
Section 32.8.17 ”DMAC Channel x [x = 0..7] Control B Register”:
- SIF bitfield description table: added DMA Master Interface references
- DIF bitfield description table: added DMA Master Interface references
Section 32.8.21 ”DMAC Write Protect Mode Register”:
- WPKEY: replaced the bitfield description with a table
8955
8835
rfo
8834
UDP:
Section 33.2 ”Embedded Characteristics”, removed references on ARM7TDMI, ARM9TDMI and AMBA from
the features list.
Added Section 33.7.11 ”UDP Endpoint Control and Status Register (Isochronous Endpoints)” describing
UDP_CSRx (ISOENDPT) alternate register.
8219
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