Datasheet

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1064
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 48-12. Min and Max access time for SPI output signal
48.15.2 SSC
48.15.2.1 Timing conditions
Timings are given assuming a capacitance load on
Table 48-33.
These values may be product dependant and should be confirmed by the specification.
SPI
10
MOSI Setup time before SPCK falls 2.4 ns
SPI
11
MOSI Hold time after SPCK falls 0.7 ns
SPI
12
NPCS0 setup to SPCK rising 4.5 ns
SPI
13
NPCS0 hold after SPCK falling 0 ns
SPI
14
NPCS0 setup to SPCK falling 3.9 ns
SPI
15
NPCS0 hold after SPCK rising 0 ns
SPI
16
NPCS0 falling to MISO valid 17.3 ns
Table 48-32. SPI Timings with 1.8V Peripheral Supply
Symbol Parameter Cond Min Max Units
SPCK
MISO
MOSI
SPI
2max
SPI
0
SPI
1
SPI
2min
Table 48-33. Capacitance Load
Corner
Supply MAX MIN
3.3V 30pF 5 pF
1.8V 20pF 5 pF