ARM-based Embedded MPU SAM9N12/SAM9CN11/SAM9CN12 DATASHEET Description Based on the ARM926EJ-S™ processor, the Atmel® SAM9N12/CN11/CN12 devices offer the frequently-requested combination of user interface functionality and high data rate connectivity, with LCD Controller, resistive touch-screen, multiple UARTs, SPI, I2C, full-speed USB Host and Device and SDIO. The SAM9N12/CN11/CN12 support the latest generation of LPDDR/DDR2 and NAND Flash memory interfaces for program and data storage.
1.
Cryptography TRNG True Random Number Generator compliant with NIST Special Publication 800-22 AES 256-, 192-, 128-bit Key Algorithm compliant with FIPS Publication 197 (except for SAM9N12) 256 Fuse bits for crypto key and 64 Fuse bits for device configuration, including JTAG disable and forced boot from the on-chip ROM I/O Four 32-bit Parallel Input/Output Controllers 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os Input Change Interrupt Capability on
Block Diagram PCK0-PCK1 FIQ IRQ DRXD DTXD XIN XOUT RSTC RTC RC 4 GPBR WDT PIT PMC DBGU AIC Fuse Box System Controller PLLA PLLB OSC16M 12M RC OSC 32K SHDC POR XIN32 XOUT32 SHDN WKUP VDDBU NRST POR PIOD VDDCORE PIOB PIOA DMA PIOC SPI0 SPI1 RS T TD I TD TMO TCS K RT CK JT AG S DMA AES * MMU D DCache 16 Kbytes EL FIFO DMA Peripheral Bridge I Bus Interface DMA SHA * DMA SSC HSMCI0 SD/SDIO * except SAM9N12 ROM 128 Kbytes ICache 16 Kbytes ARM926EJ-S In-Circuit Emulator
3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1.
Table 3-1.
Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Universal Asynchronous Receiver Transmitter - UARTx UTXDx UARTx Transmit Data Output URXDx UARTx Receive Data Input Synchronous Serial Controller - SSC TD SSC Transmit Data Output RD SSC Receive Data Input TK SSC Transmit Clock I/O RK SSC Receive Clock I/O TF SSC Transmit Frame Sync I/O RF SSC Receive Frame Sync I/O Timer Counter - TCx x=0..
Table 3-1.
4. Package and Pinout The SAM9CN12 is available in 217-ball and 247-ball BGA packages. 4.1 Mechanical Overview of the 217-ball BGA Package Figure 4-1 shows the orientation of the 217-ball BGA Package Figure 4-1.
4.2 Mechanical Overview of the 247-ball BGA Package Figure 4-2 shows the orientation of the 247-ball BGA Package Figure 4-2.
4.3 217-ball BGA Package Pinout Table 4-1.
Table 4-1.
Table 4-1.
Table 4-1.
Table 4-1.
Table 4-1.
4.4 247-ball BGA Package Pinout Table 4-2.
Table 4-2.
Table 4-2.
Table 4-2.
Table 4-2.
Table 4-2.
5. Power Considerations 5.1 Power Supplies The SAM9N12/CN11/CN12 has several types of power supply pins: Table 5-1. SAM9N12/CN11/CN12 Power Supplies Name Voltage Range, nominal Associated Ground VDDCORE 0.9-1.1V, 1.0V GNDCORE the core, including the processor, the embedded memories and the peripherals, the internal 12 MHz RC GNDIOM the External Memory Interface I/O lines GNDIOM the NAND Flash I/O and control, D16-D32 and multiplexed SMC lines VDDIOM VDDNF 1.65-1.95V, 1.8V 3.0-3.6V, 3.3V 1.
6. Memories Figure 6-1.
6.1 Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5.
Programmable Wait State Generation External Wait Request Programmable Data Float Time Slow Clock mode supported 6.3.
7. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories. 7.
7.2 System Controller Block DIagram Figure 7-1. SAM9N12/CN11/CN12 System Controller Block Diagram System Controller VDDCORE Powered irq fiq periph_irq[2..
7.3 7.
8. Peripherals 8.1 Peripheral Mapping As shown in Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. 8.2 Peripheral Identifiers Figure 8-1 defines the Peripheral Identifiers of the SAM9N12/CN11/CN12.
Table 8-1. SAM9N12/CN11/CN12 Peripheral Identifiers (Continued) Instance ID Instance name Instance description 26 Reserved 27 SHA Secure Hash Algorithm 28 SSC Synchronous Serial Controller 29 AES Advanced Encryption Standard 30 TRNG True Random Number Generator 31 AIC Advanced Interrupt Controller 8.3 Peripheral Interrupts and Clock Control 8.3.
‘I’/’O’ Indicates whether the signal is input or output state. “PU”/”PD” Indicates whether Pull-up or Pull-down, or nothing is enabled. “ST” Indicates if Schmitt Trigger is enabled. Note: 8.4.2 Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO Input with Pull-Up.
9. ARM926EJ-S Processor Overview 9.1 Description The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density.
16-word Data Buffer 4-address Address Buffer Software Control Drain DCache Write-back Buffer 8 Data Word Entries One Address Entry Software Control Drain Tightly-coupled Memory (TCM) Separate Instruction and Data TCM Interfaces Provides a Mechanism for DMA Support Memory Management Unit (MMU) Access Permission for Sections Access Permission for Large Pages and Small Pages 16 Embedded Domains 64 Entry Instruction TLB and 64 Entry Data TLB Memory
9.3 Block Diagram Figure 9-1.
9.4 ARM9EJ-S Processor 9.4.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: ARM state: 32-bit, word-aligned ARM instructions. THUMB state: 16-bit, halfword-aligned Thumb instructions. Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 9.4.
9.4.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: User mode is the usual ARM program execution state. It is used for executing most application programs Fast Interrupt (FIQ) mode is used for handling fast interrupts.
The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed.
The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where: 9.4.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR.
Table 9-2.
9.4.11 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: Branch instructions Data processing instructions Load and Store instructions Load and Store multiple instructions Exception-generating instruction Table 9-4 gives the Thumb instruction mnemonic list. Table 9-4.
9.5 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: ARM9EJ-S Caches (ICache, DCache and write buffer) TCM MMU Other system options To control these features, CP15 provides 16 additional registers. See Table 9-5. Table 9-5.
9.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
9.6 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13.
9.6.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort.
9.7.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address.
9.7.2.4 Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 9.8 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests.
10. Debug and Test 10.1 Description The SAM9CN12 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.
Block Diagram Figure 10-1. Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset ARM9EJ-S ICE-RT ARM926EJ-S DMA DBGU PIO 10.
10.4 Application Examples 10.4.1 Debug Environment Figure 10-2 on page 51 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 10-2.
10.4.2 Test Environment Figure 10-3 on page 52 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n AT91SAM9 Chip 2 Chip 1 AT91SAM9-based Application Board In Test 10.
10.6 Functional Description 10.6.1 EmbeddedICE The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus.
10.6.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations.
11. Advanced Interrupt Controller (AIC) 11.1 Description The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
11.3 Block Diagram Figure 11-1. Block Diagram FIQ AIC ARM Processor IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 11.4 Application Block Diagram Figure 11-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 11.
11.6 I/O Line Description Table 11-1. I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0 - IRQn Interrupt 0 - Interrupt n Input 11.7 Product Dependencies 11.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function.
11.8 Functional Description 11.8.1 Interrupt Source Control 11.8.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
Figure 11-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Edge Fast Interrupt Controller or Priority Controller AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR Figure 11-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg. Edge Detector Set FF Clear AIC_IDCR AIC_ISCR AIC_ICCR 11.8.
Figure 11-6. External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles Figure 11-7. External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles Figure 11-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.
11.8.3 Normal Interrupt 11.8.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest.
This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 11.8.3.4 Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits.
11.8.4 Fast Interrupt 11.8.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. 11.8.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller.
6. Note: Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. The “F” bit in SPSR is significant.
11.8.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR.
11.8.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode.
11.10 Advanced Interrupt Controller (AIC) User Interface 11.10.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset. Table 11-3.
11.10.2 AIC Source Mode Register Name: AIC_SMR0..AIC_SMR31 Address: 0xFFFFF000 Access Read-write Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – SRCTYPE PRIOR This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register.
11.10.3 AIC Source Vector Register Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register. • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.
11.10.4 AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF100 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt.
11.10.5 AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF104 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
11.10.6 AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF108 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – IRQID • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number.
11.10.
11.10.
11.10.9 AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF114 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ • NFIQ: NFIQ Status 0: nFIQ line is deactivated. 1: nFIQ line is active. • NIRQ: NIRQ Status 0: nIRQ line is deactivated. 1: nIRQ line is active.
11.10.10 AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF120 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Enable 0: No effect.
11.10.11 AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF124 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Disable 0: No effect.
11.10.12 AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF128 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Clear 0: No effect.
11.10.13 AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF12C Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Set 0: No effect.
11.10.14 AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF130 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – – The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
11.10.15 AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF134 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register.
11.10.16 AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF138 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – GMSK PROT This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register • PROT: Protection Mode 0: The Protection Mode is disabled.
11.10.17 AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF140 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Enable 0: No effect.
11.10.18 AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF144 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Disable 0: No effect.
11.10.
11.10.20 AIC Write Protect Mode Register Name: AIC_WPMR Address: 0xFFFFF1E4 Access: Read-write Reset: See Table 11-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII).
11.10.21 AIC Write Protect Status Register Name: AIC_WPSR Address: 0xFFFFF1E8 Access: Read-only Reset: See Table 11-3 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the AIC_WPSR register.
12. Boot Strategies 12.1 SAM9CN12 only The SAM9CN12 embeds a Secure Boot allowing firmware stored in external Non-Volatile Memory to be protected. The content of the external NVM is encrypted and signed based using a 256-bit AES algorithm. Prior to booting from the externally stored firmware, the secure boot will authenticate the firmware, decrypt it and store it in on-chip memory. Access to the on-chip memory is prevented and the maximum size of the firmware should not exceed 24 kB.
12.2.2 Flow Diagram The ROM Code implements the algorithm shown below in Figure 12-1. Figure 12-1. ROM Code Algorithm Flow Diagram Chip Setup Valid boot code found in one NVM Yes Copy and run it in internal SRAM No SAM-BA Monitor 12.2.3 Chip Setup At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz Fast RC Oscillator. Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode. 2.
12.2.4 NVM Boot 12.2.4.1 NVM Boot Sequence The boot sequence on external memory devices can be controlled using the Boot Sequence Register (BSCR). The 3 LSBs of the BSCR are available to control the sequence. The user can then choose to bypass some steps shown in Figure 12-2 “NVM Bootloader Sequence Diagram” according to the BSCR Value. Table 12-2.
Figure 12-2.
12.2.4.2 NVM Bootloader Program Description Figure 12-3. NVM Bootloader Program Diagram Start Initialize NVM Initialization OK ? No Restore the reset values for the peripherals and Jump to next boot solution Yes Valid code detection in NVM NVM contains valid code No Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals.
If a valid code is found, this code is loaded from NVM into internal SRAM and executed by branching at address 0x0000_0000 after remap. This code may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. Figure 12-4. Remap Action after Download Completion 0x0000_0000 0x0000_0000 REMAP Internal ROM Internal SRAM 0x0010_0000 0x0010_0000 Internal ROM Internal ROM 0x0030_0000 0x0030_0000 Internal SRAM Internal SRAM 12.2.4.
The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with the user’s own vector. This information is described below. Figure 12-7. Structure of the ARM Vector 6 31 0 Size of the code to download in bytes The value has to be smaller than 24 kbytes. This size is the internal SRAM size minus the stack size used by the ROM Code at the end of the internal SRAM.
Figure 12-8. Boot NAND Flash Download Start Initialize NAND Flash interface Send Reset command No First page contains valid header Yes NAND Flash is ONFI Compliant No Yes Read NAND Flash and PMECC parameters from the header Read NAND Flash and PMECC parameters from the ONFI Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals.
NAND Flash Specific Header Detection This is the first method used to determine NAND Flash parameters. After Initialization and Reset command, the Boot Program reads the first page without ECC check, to determine if the NAND parameter header is present. The header is made of 52 times the same 32-bit word (for redundancy reasons) which must contain NAND and PMECC parameters used to correctly perform the read of the rest of the data in the NAND.
ONFI 2.2 Parameters In case no valid header has been found, the Boot Program will check if the NAND Flash is ONFI compliant, sending a Read Id command (0x90) with 0x20 as parameter for the address.
The PMECC descriptor structure is: typedef struct _PMECC_paramDesc_struct { unsigned int pageSize; unsigned int spareSize; unsigned int sectorSize; // 0 for 512, 1 for 1024 bytes unsigned int errBitNbrCapability; unsigned int eccSizeByte; unsigned int eccStartAddr; unsigned int eccEndAddr; unsigned unsigned unsigned unsigned unsigned int int int int int nandWR; spareEna; modeAuto; clkCtrl; interrupt; int tt; int mm; int nn; short *alpha_to; short *index_of; short partialSyn[100]; short si[100]; /* sigma
The Galois field tables are mapped in the ROM just after the ROM code, as described in Figure 12-9 below: Figure 12-9. Galois Field Table Mapping 0x0010_0000 ROM Code 0x0010_8000 0x0011_0000 Galois field tables for 512-byte sectors correction Galois field tables for 1024-byte sectors correction For a full description and an example of how to use the PMECC detection and correction feature, refer to the software package dedicated to this device on Atmel’s web site.
Supported DataFlash Devices The SPI Flash Boot program supports all Atmel DataFlash devices. Table 12-3.
12.2.4.5 Hardware and Software Constraints The NVM drivers use several PIOs in peripheral mode to communicate with external memory devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between output pins used by the NVM drivers and the connected devices may occur. To assure correct functionality, it is recommended to plug in critical devices to other pins not used by NVM.
12.2.5 SAM-BA Monitor If no valid code has been found in NVM during the NVM bootloader sequence, the SAM-BA Monitor program is launched. The SAM-BA Monitor principle is to: Initialize DBGU and USB Check if USB Device enumeration has occurred Check if characters have been received on the DBGU Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in Table 12-5. Figure 12-10.
12.2.5.1 Command List Table 12-5.
12.2.5.2 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115,200 Baud, 8 bits of data, no parity, 1 stop bit. Supported External Crystal/External Clocks The SAM-BA Monitor supports a frequency of 12 MHz to allow DBGU communication for both external crystal and external clock. Xmodem Protocol The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target.
12.2.5.3 USB Device Port Supported External Crystal / External Clocks The frequencies supported by SAM-BA Monitor to allow USB communication are 4, 8, 12 or 16 MHz crystal or external clock. USB Class The device uses the USB Communication Device Class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ®, from Windows 98SE® to Windows XP®. The CDC document, available at www.usb.
13. Boot Sequence Controller (BSC) 13.1 Description The System Controller embeds a Boot Sequence Configuration Register (BSC_CR) to save timeout delays on boot. The boot sequence is programmable through the BSC_CR. The BSC_CR is powered by VDDBU. Any modification of the register value is stored and applied after the next reset. The register defaults to the factory value in case of battery removal. The BSC_CR is programmable with user programs or SAM-BA and is key-protected. 13.
13.4 Boot Sequence Controller (BSC) Registers User Interface Table 13-1. Register Mapping Offset 0x0 Register Name Boot Sequence Configuration Register BSC_CR Access Reset Read-write – 13.4.
14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.
14.3 Block Diagram Figure 14-1.
14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: proc_nreset: Processor reset line. It also resets the Watchdog Timer. backup_nreset: Affects all the peripherals powered by VDDBU. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin.
14.4.2.1 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in the RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
Figure 14-4. General Reset State SLCK Any Freq.
14.4.4.2 Wake-up Reset The wake-up reset occurs when the main supply is down. When the main supply POR output is active, all the reset signals are asserted except backup_nreset. When the main supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise.
14.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin When a falling edge occurs on NRST (reset activation), internal reset lines are immediately asserted. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
14.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
14.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. If WDRPROC = 1, only the processor reset is asserted.
14.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: Backup Reset Wake-up Reset User Reset Watchdog Reset Software Reset Particular cases are listed below: When in User Reset: A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated.
14.5 Reset Controller (RSTC) User Interface Table 14-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 Note: Access Reset Back-up Reset RSTC_CR Write-only - - Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read-write - 0x0000_0000 1. The reset value of RSTC_SR either reports a general reset or a wake-up reset depending on last rising power supply.
14.5.
14.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFE04 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
14.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFE08 Access: Read-write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 – KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 – 3 – ERSTL 2 – • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows the assertion duration to be programmed between 60 µs and 2 seconds.
15. Real-time Clock (RTC) 15.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
15.3 Block Diagram Figure 15-1. RTC Block Diagram 15.4 Slow Clock: SLCK 32768 Divider Bus Interface Bus Interface Time Date Entry Control Interrupt Control RTC Interrupt Product Dependencies 15.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 15.4.2 Interrupt Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts.
15.5 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099. 15.5.
The following checks are performed: 1. Century (check if it is in range 19 - 20 ) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”) 5. Day (check range 1 - 7) 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8.
Figure 15-2.
15.6 Real-time Clock (RTC) User Interface Table 15-1.
15.6.1 RTC Control Register Name: RTC_CR Address: 0xFFFFFEB0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0: No effect. 1: Stops the RTC time counting. Time counting consists of second, minute and hour counters.
15.6.2 RTC Mode Register Name: RTC_MR Address: 0xFFFFFEB4 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected. 1: 12-hour mode is selected.
15.6.3 RTC Time Register Name: RTC_TIMR Address: 0xFFFFFEB8 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units.
15.6.4 RTC Calendar Register Name: RTC_CALR Address: 0xFFFFFEBC Access: Read-write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (gregorian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units.
15.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0xFFFFFEC0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 6 5 SECEN Note: 11 MIN 4 3 SEC To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_TIMALR register.
15.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0xFFFFFEC4 Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 15 14 13 12 11 10 9 8 – – – – – – – – Note: 20 19 MONTH 7 6 5 4 3 2 1 0 – – – – – – – – To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made.
15.6.7 RTC Status Register Name: RTC_SR Address: 0xFFFFFEC8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 (FREERUN): Time and calendar registers cannot be updated. 1 (UPDATE): Time and calendar registers can be updated.
15.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0xFFFFFECC Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0: No effect.
15.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0xFFFFFED0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0: No effect.
15.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0xFFFFFED4 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0: No effect.
15.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0xFFFFFED8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled.
15.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0xFFFFFEDC Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed.
16. Periodic Interval Timer (PIT) 16.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.
16.3 Block Diagram Figure 16-1.
16.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
16.5 Periodic Interval Timer (PIT) User Interface Table 16-1.
16.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFE30 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
16.5.2 Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFE34 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0: The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1: The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
16.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFE38 Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.
16.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFE3C Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer (WDT) can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 17.
17.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
Figure 17-2.
17.5 Watchdog Timer (WDT) User Interface Table 17-1.
17.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0xFFFFFE40 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog if KEY is written to 0xA5. • KEY: Password. Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation.
17.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0xFFFFFE44 Access: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 18 11 10 22 26 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV Note: The first write access prevents any further modification of the value of this register, read accesses remain possible.
• WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.
17.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0xFFFFFE48 Access Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
18. Shutdown Controller (SHDWC) 18.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 18.2 Embedded Characteristics 18.3 Shutdown and Wake-up Logic Software Assertion of the SHDW Output Pin Programmable De-assertion from the WKUP Input Pins Block Diagram Figure 18-1.
18.5 Product Dependencies 18.5.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller. 18.6 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN.
18.7 Shutdown Controller (SHDWC) User Interface Table 18-2.
18.7.1 Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFE10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW • SHDW: Shutdown Command 0: No effect. 1: If KEY is correct, asserts the SHDN pin. • KEY: Password Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation.
18.7.
18.7.3 Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFE18 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWK 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 • WAKEUP0: Wake-up 0 Status 0: No wake-up event occurred on WKUP0 input since the last read of SHDW_SR. 1: At least one wake-up event occurred on WKUP0 input since the last read of SHDW_SR.
19. General-Purpose Backup Registers (GPBR) 19.1 Description The System Controller embeds four General-purpose Backup registers. 19.2 Embedded Characteristics 19.3 Four 32-bit General Purpose Backup Registers General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset 0x0 ... 0xc Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 3 SYS_GPBR3 Access Reset Read-write – ... ... Read-write – 19.3.
20. Slow Clock Controller (SCKC) 20.1 Description The System Controller embeds a Slow Clock Controller. The slow clock can be generated either by an external 32768 Hz crystal oscillator or by the on-chip 32 kHz RC oscillator. The 32768 Hz crystal oscillator can be bypassed by setting the OSC32BYP bit to accept an external slow clock on XIN32.
20.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator To switch from the internal 32 kHz RC oscillator to the 32768 Hz crystal oscillator, the programmer must execute the following sequence: Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller. Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1. Wait 32768 Hz startup time for clock stabilization (software loop).
20.4 Slow Clock Controller (SCKC) User Interface Table 20-1.
20.4.1 Slow Clock Configuration Register Name: SCKC_CR Address: 0xFFFFFE50 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCSEL 2 OSC32BYP 1 OSC32EN 0 RCEN • RCEN: Internal 32 kHz RC Oscillator 0: 32 kHz RC oscillator is disabled. 1: 32 kHz RC oscillator is enabled. • OSC32EN: 32768 Hz Oscillator 0: 32768 Hz oscillator is disabled.
21. Clock Generator 21.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 22.12 “Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 21.
21.3 Block Diagram Figure 21-1.
21.4 Slow Clock Selection The slow clock can be generated either by an external 32,768 Hz crystal or by the on-chip 32 kHz RC oscillator. The 32,768 Hz crystal oscillator can be bypassed by setting the bit OSC32BYP to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32,768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source. Figure 21-2.
21.4.2 Bypass the 32768 Hz Oscillator The following step must be added to bypass the 32768 Hz Oscillator. An external clock must be connected on XIN32. Enable the bypass path OSC32BYP bit set to 1. Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0. 21.4.3 Switch from the 32,768 Hz Crystal to Internal 32 kHz RC Oscillator The same procedure must be followed to switch from a 32,768 Hz crystal to the internal 32 kHz RC oscillator.
21.4.
21.5 Main Clock Figure 21-3.
21.5.1 12 MHz Fast RC Oscillator After reset, the 12 MHz Fast RC Oscillator is enabled and it is selected as the source of MCK. MCK is the default clock selected to start up the system. Please refer to the “DC Characteristics” section of the product datasheet. The software can disable or enable the 12 MHz Fast RC Oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator Register (CKGR_MOR).
21.5.5 Software Sequence to Detect the Presence of Fast Crystal The frequency meter carried on CKGR_MCFR register is operating on the selected main clock and not on fast crystal clock nor fast RC Oscillator clock. Therefore, to check for the presence of a fast crystal clock, it is necessary to switch the main clock on fast crystal clock.
21.6 Divider and PLL Block The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider. Figure 21-4 shows the block diagram of the divider and PLL block. Figure 21-4. Divider and PLL Block Diagram DIVB MULB Divider B MAINCK DIVA PLL B MULA Divider A OUTB PLLBCK OUTA PLL A PLLACK PLLBCOUNT PLL B Counter LOCKB PLLACOUNT SLCK PLL A Counter LOCKA 21.6.
22. Power Management Controller (PMC) 22.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core. 22.2 Embedded Characteristics The Power Management Controller provides all the clock signals to the system. PMC input clocks: PLLACK: From PLLA PLLBCK: From PLLB and dedicated to USB clock generation.
22.3 Block Diagram Figure 22-1. General Clock Block Diagram PLLACK Processor Clock Controller PCK int Divider /1,/2 PLLBCK MAINCK SLCK Prescaler /1,/2,/4,.../64 X /1 /1.5 /2 SysClk DDR /1 /2 /3 /4 MCK Peripherals Clock Controller ON/OFF Master Clock Controller SLCK MAINCK Divider periph_clk[..] ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] PLLBCK Programmable Clock Controller 22.4 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK).
22.5 Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock (PCK) is enabled after a reset and is automatically re-enabled by any enabled interrupt.
22.8 Peripheral Clock Controller The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral Clock Controller. The user can individually enable and disable the clock on the peripherals and select a division factor from MCK. This is done through the Peripheral Control Register (PMC_PCR). In order to save power consumption, the division factor can be 1, 2, 4 or 8. PMC_PCR is a register that features a command and acts like a mailbox.
22.10 Programming Sequence 1. Enabling the 12 MHz Main Oscillator: The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR register. Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set.
Code Example: write_register(CKGR_PLLBR,0x00040805) 4. If PLL B and divider B are enabled, the PLL B input clock is the main clock. PLL B output clock is PLL B input clock multiplied by 5. Once CKGR_PLLBR has been written, LOCKB bit will be set after eight slow clock cycles. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers.
5. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 2 programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled. PMC_PCKx registers are used to configure programmable clocks.
22.11 Clock Switching Details 22.11.1 Master Clock Switching Timings Table 22-1 and Table 22-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 22-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock Main Clock – 4 x SLCK + 2.5 x Main Clock SLCK 0.
22.11.2 Clock Switching Waveforms Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 22-4.
Figure 22-5. Change PLLA Programming Slow Clock PLLA Clock LOCKA MCKRDY Master Clock Slow Clock Write CKGR_PLLAR Figure 22-6.
22.12 Power Management Controller (PMC) User Interface Table 22-3. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only N.A. 0x0004 System Clock Disable Register PMC_SCDR Write-only N.A. 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0005 0x0010 Peripheral Clock Enable Register PMC _PCER Write-only N.A.
22.12.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – LCDCK DDRCK – – • DDRCK: DDR Clock Enable 0: No effect. 1: Enables the DDR clock. • LCDCK: LCD Clock Enable 0: No effect. 1: Enables the LCD clock.
22.12.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – LCDCK DDRCK – PCK • PCK: Processor Clock Disable 0: No effect. 1: Disables the Processor clock. This is used to enter the processor in Idle Mode. • DDRCK: DDR Clock Disable 0: No effect.
22.12.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – LCDCK DDRCK – PCK • PCK: Processor Clock Status 0: The Processor clock is disabled. 1: The Processor clock is enabled. • DDRCK: DDR Clock Status 0: The DDR clock is disabled.
22.12.4 PMC Peripheral Clock Enable Register Name: PMC_PCER Address: 0xFFFFFC10 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0: No effect.
22.12.5 PMC Peripheral Clock Disable Register Name: PMC_PCDR Address: 0xFFFFFC14 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Disable 0: No effect.
22.12.
22.12.7 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 CFDEN 24 MOSCSEL 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 – 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 – 5 – 4 – • KEY: Password Should be written at value 0x37. Writing any other value in this field aborts the write operation.
22.12.8 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 RCMEAS 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINFRDY: Main Clock Ready 0: MAINF value is not valid or the Main Oscillator is disabled.
22.12.9 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read-write 31 – 30 – 29 1 28 – 23 22 21 20 27 – 26 25 MULA 24 19 18 17 16 10 9 8 2 1 0 MULA 15 14 13 12 11 OUTA 7 PLLACOUNT 6 5 4 3 DIVA Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register. • DIVA: Divider A 0: Divider output is 0.
22.12.10 PMC Clock Generator PLLB Register Name: CKGR_PLLBR Address: 0xFFFFFC2C Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 25 MULB 24 19 18 17 16 10 9 8 2 1 0 MULB 15 14 13 12 11 OUTB 7 PLLBCOUNT 6 5 4 3 DIVB Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC. • DIVB: Divider B 0: Divider output is 0. 1: Divider is bypassed.
22.12.
• MDIV: Master Clock Division Value Name 0 EQ_PCK 1 PCK_DIV2 2 PCK_DIV4 3 PCK_DIV3 Description Master Clock is Prescaler Output Clock divided by 1. Warning: DDRCK is not available. Master Clock is Prescaler Output Clock divided by 2. DDRCK is equal to MCK. Master Clock is Prescaler Output Clock divided by 4. DDRCK is equal to MCK. Master Clock is Prescaler Output Clock divided by 3. DDRCK is equal to MCK.
22.12.12 USB Clock Register Name: PMC_USB Address: 0xFFFFFC38 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – USBDIV 7 6 5 4 3 2 1 0 – – – – – – – USBS • USBS: USB OHCI Input Clock Selection 0: USB Clock disabled. 1: USB Clock Input is PLLB. • USBDIV: Divider for USB Clock USB Clock is Input Clock divided by USBDIV+1.
22.12.
22.12.
22.12.
22.12.16 PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – FOS CFDS CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 – – – – – – PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 OSCSELS – – – MCKRDY LOCKB LOCKA MOSCXTS • MOSCXTS: Main XTAL Oscillator Status 0: Main XTAL oscillator is not stabilized. 1: Main XTAL oscillator is stabilized.
• CFDEV: Clock Failure Detector Event 0: No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. 1: At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. • CFDS: Clock Failure Detector Status 0: A clock failure of the main on-chip RC oscillator clock is not detected. 1: A clock failure of the main on-chip RC oscillator clock is detected.
22.12.
22.12.
22.12.19 PMC Write Protect Mode Register Name: PMC_WPMR Address: 0xFFFFFCE4 Access: Read-write Reset: See Table 22-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
22.12.20 PMC Write Protect Status Register Name: PMC_WPSR Address: 0xFFFFFCE8 Access: Read-only Reset: See Table 22-3 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
22.12.21 PMC Peripheral Control Register Name: PMC_PCR Address: 0xFFFFFD0C Access: Write-only 31 – 30 – 29 – 28 EN 27 – 26 – 25 – 23 – 22 – 21 – 20 – 19 – 18 – 17 15 – 14 – 13 – 12 CMD 11 – 10 – 9 – 8 – 7 – 6 – 5 4 3 2 1 0 24 – 16 DIV PID • PID: Peripheral ID Peripheral ID selection from PID2 to PID31 PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. • CMD: Command 0: Read mode. 1: Write mode.
23. Parallel Input/Output Controller (PIO) 23.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of the product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface.
23.3 Block Diagram Figure 23-1. Block Diagram PIO Controller Interrupt Controller PIO Interrupt PIO Clock PMC Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 23-2.
23.4 Product Dependencies 23.4.1 Pin Multiplexing Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e.
23.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 23-3. In this description each signal shown represents one of up to 32 possible indexes. Figure 23-3.
23.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing to the Pull-up Enable register (PIO_PUER) or Pull-up Disable register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in the Pull-up Status register (PIO_PUSR).
23.5.4 Output Control When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 determines whether the pin is driven or not. When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing the Output Enable register (PIO_OER) and Output Disable register (PIO_ODR).
Figure 23-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 23.5.8 Inputs The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral.
Figure 23-5. Input Glitch Filter Timing PIO_IFCSR = 0 MCK up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles 1 cycle up to 2.5 cycles PIO_PDSR if PIO_IFSR = 1 up to 2 cycles Figure 23-6. Input Debouncing Filter Timing PIO_IFCSR = 1 Divided Slow Clock Pin Level up to 2 cycles Tmck up to 2 cycles Tmck PIO_PDSR if PIO_IFSR = 0 1 cycle Tdiv_slclk 1 cycle Tdiv_slclk up to 1.5 cycles Tdiv_slclk PIO_PDSR if PIO_IFSR = 1 up to 1.
In order to select an additional interrupt mode: The type of event detection (edge or level) must be selected by writing in the Edge Select register (PIO_ESR) and Level Select register (PIO_LSR) which , respectively, the edge and level detection. The current status of this selection is accessible through the Edge/Level Status register (PIO_ELSR).
23.5.10.2 Interrupt Mode Configuration All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. 23.5.10.3 Edge or Level Detection Configuration Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR. The other lines are configured in edge detection by default, if they have not been previously configured.
Figure 23-9. Programmable I/O Delays PIO PAin[0] PAout[0] Programmable Delay Line DELAY1 PAin[1] PAout[1] Programmable Delay Line DELAY2 PAin[2] PAout[2] Programmable Delay Line DELAYx 23.5.12 Programmable I/O Drive It is possible to configure the I/O drive for pads PA[31:0], PB[18:0], PC[31:0]. For any details, refer to the product electrical characteristics. 23.5.13 Programmable Schmitt Trigger It is possible to configure each input for the Schmitt trigger.
23.6 I/O Lines Programming Example The programming example shown in Table 23-1 is used to obtain the following configuration.
23.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns one systematically. Table 23-2.
Table 23-2.
23.7.
23.7.3 PIO Status Register Name: PIO_PSR Addresses: 0xFFFFF408 (PIOA), 0xFFFFF608 (PIOB), 0xFFFFF808 (PIOC), 0xFFFFFA08 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active).
23.7.
23.7.6 PIO Output Status Register Name: PIO_OSR Addresses: 0xFFFFF418 (PIOA), 0xFFFFF618 (PIOB), 0xFFFFF818 (PIOC), 0xFFFFFA18 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Status 0: The I/O line is a pure input.
23.7.
23.7.
23.7.10 PIO Set Output Data Register Name: PIO_SODR Addresses: 0xFFFFF430 (PIOA), 0xFFFFF630 (PIOB), 0xFFFFF830 (PIOC), 0xFFFFFA30 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0: No effect.
23.7.
23.7.13 PIO Pin Data Status Register Name: PIO_PDSR Addresses: 0xFFFFF43C (PIOA), 0xFFFFF63C (PIOB), 0xFFFFF83C (PIOC), 0xFFFFFA3C (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The I/O line is at level 0.
23.7.14 PIO Interrupt Enable Register Name: PIO_IER Addresses: 0xFFFFF440 (PIOA), 0xFFFFF640 (PIOB), 0xFFFFF840 (PIOC), 0xFFFFFA40 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Enable 0: No effect.
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23.7.20 PIO Multi-driver Status Register Name: PIO_MDSR Addresses: 0xFFFFF458 (PIOA), 0xFFFFF658 (PIOB), 0xFFFFF858 (PIOC), 0xFFFFFA58 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi-Drive Status 0: The multi-drive is disabled on the I/O line.
23.7.
23.7.23 PIO Pull-Up Status Register Name: PIO_PUSR Addresses: 0xFFFFF468 (PIOA), 0xFFFFF668 (PIOB), 0xFFFFF868 (PIOC), 0xFFFFFA68 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull-Up Status 0: Pull-up resistor is enabled on the I/O line.
23.7.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” .
23.7.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Peripheral Select.
23.7.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Addresses: 0xFFFFF480 (PIOA), 0xFFFFF680 (PIOB), 0xFFFFF880 (PIOC), 0xFFFFFA80 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Clock Glitch Filtering Select 0: No effect.
23.7.
23.7.29 PIO Slow Clock Divider Debouncing Register Name: PIO_SCDR Addresses: 0xFFFFF48C (PIOA), 0xFFFFF68C (PIOB), 0xFFFFF88C (PIOC), 0xFFFFFA8C (PIOD) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – 7 6 2 1 0 DIV 5 4 3 DIV • DIV: Slow Clock Divider Selection for Debouncing Tdiv_slclk = 2*(DIV+1)*Tslow_clock.
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23.7.
23.7.36 PIO Additional Interrupt Modes Enable Register Name: PIO_AIMER Addresses: 0xFFFFF4B0 (PIOA), 0xFFFFF6B0 (PIOB), 0xFFFFF8B0 (PIOC), 0xFFFFFAB0 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Additional Interrupt Modes Enable 0: No effect.
23.7.
23.7.39 PIO Edge Select Register Name: PIO_ESR Addresses: 0xFFFFF4C0 (PIOA), 0xFFFFF6C0 (PIOB), 0xFFFFF8C0 (PIOC), 0xFFFFFAC0 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge Interrupt Selection 0: No effect.
23.7.
23.7.
23.7.45 PIO Write Protection Mode Register Name: PIO_WPMR Addresses: 0xFFFFF4E4 (PIOA), 0xFFFFF6E4 (PIOB), 0xFFFFF8E4 (PIOC), 0xFFFFFAE4 (PIOD) Access: Read/Write Reset: See Table 23-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 5 – – 4 – – – For more information on write-protecting registers, refer to Section 23.5.14 ”Register Write Protection”.
23.7.46 PIO Write Protection Status Register Name: PIO_WPSR Addresses: 0xFFFFF4E8 (PIOA), 0xFFFFF6E8 (PIOB), 0xFFFFF8E8 (PIOC), 0xFFFFFAE8 (PIOD) Access: Read-only Reset: See Table 23-2 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 – WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – – – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PIO_WPSR register.
23.7.
23.7.48 PIO I/O Delay Register Name: PIO_DELAYR Addresses: 0xFFFFF510 (PIOA), 0xFFFFF710 (PIOB), 0xFFFFF910 (PIOC), 0xFFFFFB10 (PIOD) Access: Read/Write Reset: See Table 23-2 31 30 29 28 27 26 Delay7 23 22 21 20 19 18 Delay5 15 14 13 6 24 17 16 9 8 1 0 Delay4 12 11 10 Delay3 7 25 Delay6 Delay2 5 4 3 Delay1 2 Delay0 • Delayx [x=0..7]: Delay Control for Simultaneous Switch Reduction Gives the number of elements in the delay line associated to pad x.
23.7.49 PIO I/O Drive Register 1 Name: PIO_DRIVER1 Addresses: 0xFFFFF514 (PIOA), 0xFFFFF714 (PIOB), 0xFFFFF914 (PIOC), 0xFFFFFB14 (PIOD) Access: Read/Write Reset: See Table 23-2 31 30 29 LINE15 23 22 21 LINE11 15 28 14 20 13 19 6 12 5 18 11 17 9 8 LINE4 2 LINE1 16 LINE8 10 3 24 LINE12 LINE5 4 LINE2 25 LINE9 LINE6 LINE3 26 LINE13 LINE10 LINE7 7 27 LINE14 1 0 LINE0 • LINEx [x=0..
23.7.50 PIO I/O Drive Register 2 Name: PIO_DRIVER2 Addresses: 0xFFFFF518 (PIOA), 0xFFFFF718 (PIOB), 0xFFFFF918 (PIOC), 0xFFFFFB18 (PIOD) Access: Read/Write Reset: See Table 23-2 31 30 29 LINE31 23 22 21 LINE27 15 27 14 20 13 19 6 12 5 18 11 17 9 8 LINE20 2 LINE17 16 LINE24 10 3 24 LINE28 LINE21 4 LINE18 25 LINE25 LINE22 LINE19 26 LINE29 LINE26 LINE23 7 28 LINE30 1 0 LINE16 • LINEx [x=16..
24. Debug Unit (DBGU) 24.1 Description The Debug Unit (DBGU) provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication.
24.3 Block Diagram Figure 24-1. Debug Unit Functional Block Diagram Peripheral Bridge (Peripheral) DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive DRXD COMMRX ARM Processor COMMTX DCC Handler Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 24-1.
24.4 Product Dependencies 24.4.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. Table 24-2. I/O Lines Instance Signal I/O Line Peripheral DBGU DRXD PA9 A DBGU DTXD PA10 A 24.4.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller.
Figure 24-3. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 24.5.2 Receiver 24.5.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
Figure 24-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 24.5.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 24-6.
24.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 24-9.
When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 24-11. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 S Data 0 Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 24.5.
Figure 24-12. Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter TXD VDD Disabled Disabled RXD TXD 24.5.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
24.5.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
24.6 Debug Unit (DBGU) User Interface Table 24-3.
24.6.1 Debug Unit Control Register Name: DBGU_CR Address: 0xFFFFF200 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
24.6.
24.6.
24.6.
24.6.
24.6.6 Debug Unit Status Register Name: DBGU_SR Address: 0xFFFFF214 Access: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
24.6.7 Debug Unit Receiver Holding Register Name: DBGU_RHR Address: 0xFFFFF218 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set. 24.6.
24.6.
24.6.10 Debug Unit Chip ID Register Name: DBGU_CIDR Address: 0xFFFFF240 Access: Read-only 31 30 29 EXT 23 28 27 26 NVPTYP 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 EPROC 3 2 VERSION • VERSION: Version of the Device Values depend upon the version of the device.
• NVPSIZ2: Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 – Reserved 5 64K 64 Kbytes 6 Reserved 7 128K 128 Kbytes 8 – Reserved 9 256K 256 Kbytes 10 512K 512 Kbytes 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved • SRAMSIZ: Internal SRAM Size Value Name Description 0 – Reserved 1 1K 1 Kbytes 2 2K 2 Kbytes 3 6K 6 Kbytes 4 112K 112 Kby
• ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx AT91SAM7AQxx Series 0x63 AT91x63 AT91x63 Series 0x70 AT91SAM7Sxx AT91SAM7Sxx Series 0x71 AT91SAM7XCxx AT91S
• NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory ROM and Embedded Flash Memory 3 ROM_FLASH NVPSIZ is ROM size NVPSIZ2 is Flash size • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists.
24.6.11 Debug Unit Chip ID Extension Register Name: DBGU_EXID Address: 0xFFFFF244 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
24.6.12 Debug Unit Force NTRST Register Name: DBGU_FNR Address: 0xFFFFF248 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST • FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low.
25. Fuse Controller (FUSE) 25.1 Description The Fuse Controller (FUSE) supports software fuse programming through a 32-bit register, only fuses set to level “1” are programmed. It reads the fuse states on startup and stores them into 32-bit registers. The first 8 Fuse Status registers (FUSE_SRx) can be masked and will read as a value of “0” regardless of the fuse state when masked. 25.2 25.
25.4 Functional Description 25.4.1 Fuse Reading The fuse states are automatically read on CORE startup and are available for reading in the 10 Fuse Status (FUSE_SRx) registers. The fuse states of bits 31 to 0 will be available at FUSE_SR0, the fuse states of bits 63 to 32 will be available at FUSE_SR1 and so on. FUSE_SRx registers can be updated manually by using the RRQ bit of the Fuse Control register (FUSE_CR).
Figure 25-3. Fuse Write Clock WSEL DATA XX 00 XX 01 Fuse[31:0] Fuse[63:32] WRQ WS RS 25.4.3 Fuse Masking It is possible to mask the first 8 FUSE_SRx registers so that they will be read at a value of “0”, regardless of the fuse state. To activate fuse masking on the first 8 FUSE_SRx registers, the MSK bit of the Fuse Mode register (FUSE_MR) must be written to level “1”. The MSK bit is write-only. Solely a general reset can disable fuse masking.
25.5 Fuse Controller (FUSE) User Interface Table 25-1. Register Mapping Offset Register Name Access Reset 0x00 Fuse Control Register FUSE_CR Write-only – 0x04 Fuse Mode Register FUSE_MR Write-only – 0x08 Fuse Index Register FUSE_IR Read-write 0x00000000 0x0C Fuse Data Register FUSE_DR Read-write – 0x10 Fuse Status Register 0 FUSE_SR0 Read-only 0x00000000 0x14 Fuse Status Register 1 FUSE_SR1 Read-only 0x00000000 ... ... ... FUSE_SR9 Read-only 0x00000000 ... 0x34 ..
25.5.1 Fuse Control Register Name: FUSE_CR Address: 0xFFFFDC00 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 RRQ 0 WRQ KEY 7 – 6 – 5 – 4 – • WRQ: Write Request 0: No effect. 1: Request the word DATA to be programmed, ignored if KEY field is not filled with 0xFB. • RRQ: Read Request 0: No effect. 1: Requests the fuses to be read and FUSE_SRx registers are then updated.
25.5.2 Fuse Mode Register Name: FUSE_MR Address: 0xFFFFDC04 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MSK • MSK: Mask Fuse Status Registers 0: No effect. 1: Masks the first 8 FUSE_SRx registers.
25.5.3 Fuse Index Register Name: FUSE_IR Address: 0xFFFFDC08 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 – 3 – 1 RS 0 WS WSEL 2 – • WS: Write Status 0: Write is pending or no write has been requested since general reset. 1: Write of fuses is done. • RS: Read Status 0: Read is pending or no read has been requested since general reset. 1: Read of fuses is done.
25.5.4 Fuse Data Register Name: FUSE_DR Address: 0xFFFFDC0C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Program Data to program. Only bits of with a value of “1” will be programmed.
25.5.5 Fuse Status Register Name: FUSE_SRx [x=0..9] Address: 0xFFFFDC10 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FUSE 23 22 21 20 FUSE 15 14 13 12 FUSE 7 6 5 4 FUSE • FUSE: Fuse Status Indicates the status of corresponding fuses: 0: Unprogrammed. 1: Programmed.
26. Bus Matrix (MATRIX) 26.1 Description The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
26.3 Matrix Masters The Bus Matrix of the AT91SAM9CN12 product manages 6 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 26-1. List of Bus Matrix Masters 26.
26.6 Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible.
This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. Every request attempted by this fixed default master will not cause any arbitration latency whereas other non privileged masters will still get one latency cycle. This technique is useful for a master that mainly perform single accesses or short bursts with some Idle cycles in between.
Use of undefined length 16-beat bursts or less is discouraged since this generally decreases significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a burst.
26.8.2.1 Fixed Priority Arbitration This arbitration algorithm is the first and only applied between masters from distinct priority pools. It is also used inside priority pools other than the highest and lowest ones (intermediate priority pools). It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the MxPR field for each master inside the MATRIX_PRAS and MATRIX_PRBS Priority Registers.
26.10 Bus Matrix (MATRIX) User Interface Table 26-4.
26.10.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0...
26.10.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...
26.10.3 Bus Matrix Priority Registers A For Slaves Name: MATRIX_PRAS0...MATRIX_PRAS4 Addresses: 0xFFFFDE80 [0], 0xFFFFDE88 [1], 0xFFFFDE90 [2], 0xFFFFDE98 [3], 0xFFFFDEA0 [4] Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – 15 14 11 10 – – – – 7 6 3 2 – – – – M5PR 13 12 M3PR 5 4 M1PR 16 M4PR 9 8 M2PR 1 0 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave.
26.10.4 Bus Matrix Master Remap Control Register Name: MATRIX_MRCR Address: 0xFFFFDF00 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 • RCBx: Remap Command Bit for Master x 0: Disables remapped address decoding for the selected Master. 1: Enables remapped address decoding for the selected Master.
26.10.5 Chip Configuration User Interface Table 26-5.
26.10.5.1 EBI Chip Select Assignment Register Name: CCFG_EBICSA Access: Read/Write Reset: 0x0000_0000 31 30 29 28 27 26 25 24 – NFD0_ON_D1 6 – – – – – – 23 22 21 20 19 18 17 16 – – – – – – EBI_DRIVE – 15 14 13 12 11 10 9 8 – – – – – – EBI_DBPDC EBI_DBPUC 7 6 5 4 3 2 1 0 – – – – EBI_CS3A – EBI_CS1A – • EBI_CS1A: EBI Chip Select 1 Assignment 0: EBI Chip Select 1 is assigned to the Static Memory Controller.
Table 26-6. Connection examples with various VDDNF and VDDIOM 1 NFD0 = D16, ..., NFD15 = D31 1.8V 1.8V DDR2 or LPDDR or LPSDR + NAND Flash 1.8V 1 NFD0 = D16, ..., NFD15 = D31 1.8V 3.3V DDR2 or LPDDR or LPSDR + NAND Flash 3.3V 1 NFD0 = D16, ..., NFD15 = D31 3.3V 1.8V 16-bit SDR + NAND Flash 1.
26.10.6 Write Protect Mode Register Name: MATRIX_WPMR Address: 0xFFFFDFE4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 26.9 “Write Protect Registers” on page 298. • WPEN: Write Protect ENable 0: Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
26.10.7 Write Protect Status Register Name: MATRIX_WPSR Address: 0xFFFFDFE8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 26.9 “Write Protect Registers” on page 298. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR.
27. External Bus Interface (EBI) 27.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, DDR, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, DDR2 and SDRAM.
27.3 EBI Block Diagram Figure 27-1.
27.4 I/O Lines Description Table 27-1.
27.5 Application Example 27.5.1 Hardware Interface Table 27-3 on page 312 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 27-3.
Table 27-4.
Table 27-4. EBI Pins and External Device Connections (Continued) Signals: EBI_ Power supply Pins of the Interfaced Device DDR2/LPDDR SDR/LPSDR NAND Flash DDRC SDRAMC NFC Controller RAS VDDIOM RAS RAS – CAS VDDIOM CAS CAS – SDWE VDDIOM WE WE – Pxx VDDNF – – CE VDDNF – – RDY Pxx Note: 1. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D7 or D16-D24 depending on memory power supplies.
27.6 Product Dependencies 27.6.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller. 27.
27.7.4 Power Supplies The product embeds a dual power supply for EBI. VDDNF for NAND Flash signals and VDDIOM for others. This allows to use an 1.8V or 3.3V NAND Flash independently of SDRAM power supply. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D15 or D16-D32 depending on memory power supplies. This switch is located in the register EBICSA in the Bus Matrix user interface.
In the following example the NAND Flash and the external RAM (DDR2 or LPDDR or 16bit LPSDR) are NOT in the same power supply range (NFD0_ON_D16 = 1). This can be used if the SMC connects to the NAND Flash only. Using this function with another device on the SMC will lead to an unpredictable behavior of that device. In that case, the default value must be selected. Figure 27-4. NAND Flash and the external RAM power supply (NFD0_ON_D16 = 1) DDR2 or LPDDR or 16-bit LPSDR (1.8V) D[15:0] D[15:0] NAND Flash (3.
27.7.5 Static Memory Controller For information on the Static Memory Controller, refer to the Static Memory Controller section. 27.7.6 DDR2SDRAM Controller For information on the DDR2SDR Controller, refer to the DDR2SDRC section. 27.7.7 Programmable Multi-bit ECC Controller For information on the PMECC Controller, refer to the PMECC section. 27.7.8 NAND Flash Support External Bus Interfaces 1 integrate circuitry that interfaces to NAND Flash devices. 27.7.8.
27.7.8.2 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines.
27.8 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 27.8.1 2x8-bit DDR2 on EBI 27.8.1.1 Hardware Configuration Figure 27-6. 2x8-bit DDR2 on EBI Configuration 27.8.1.2 Software Configuration Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Register located in the bus matrix memory space.
27.8.2 16-bit LPDDR on EBI 27.8.2.1 Hardware Configuration Figure 27-7. 16-bit LPDDR on EBI Configuration 27.8.2.2 Software Configuration The following configuration has to be performed: Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select Register located in the bus matrix memory space. Initialize the DDR2 Controller depending on the LPDDR device and system bus frequency.
27.8.3 16-bit SDRAM 27.8.3.1 Hardware Configuration Figure 27-8. 16-bit SDRAM Configuration 27.8.3.2 Software Configuration The following configuration has to be performed: Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits.
27.8.4 2x16-bit SDRAM 27.8.4.1 Hardware Configuration Figure 27-9. 2x16-bit SDRAM Configuration A[1..14] D[0..31] SDRAM MN1 VDDIOM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 23 24 25 26 29 30 31 32 33 34 22 35 BA0 BA1 20 21 A14 36 40 CKE 37 CLK 38 DQM0 DQM1 15 39 CAS RAS 17 18 WE R1 470K 16 19 MN2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
27.8.5 8-bit NAND Flash with NFD0_ON_D16 = 0 27.8.5.1 Hardware Configuration Figure 27-10. 8-bit NAND Flash with NFD0_ON_D16 = 0 D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 3V3 R1 10K R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
27.8.6 16-bit NAND Flash with NFD0_ON_D16 = 0 27.8.6.1 Hardware Configuration Figure 27-11. 16-bit NAND Flash with NFD0_ON_D16 = 0 D[0..15] U1 16 17 8 18 9 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 3V3 R1 10K R2 10K 7 19 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 MT29F2G16AABWP-ET CLE I/O0 26 ALE I/O1 28 RE I/O2 30 WE I/O3 32 CE I/O4 40 I/O5 42 R/B I/O6 44 I/O7 46 WP I/O8 27 I/O9 29 I/O10 31 N.C I/O11 33 N.C I/O12 41 N.C I/O13 43 N.C I/O14 45 N.C I/O15 47 N.C N.C N.C 39 N.C PRE 38 N.C N.C 36 N.
27.8.7 8-bit NAND Flash with NFD0_ON_D16 = 1 27.8.7.1 Hardware Configuration Figure 27-12. 8-bit NAND Flash with NFD0_ON_D16 = 1 27.8.7.2 Software Configuration The following configuration has to be performed: Set NFD0_ON_D16 = 1 in the EBI Chip Select Assignment Register located in the bus matrix memory space. Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register. Configure the PIOD controller to assign the required PIOD[23..
27.8.8 16-bit NAND Flash with NFD0_ON_D16 = 1 27.8.8.1 Hardware Configuration Figure 27-13. 16-bit NAND Flash with NFD0_ON_D16 = 1 27.8.8.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller.
27.8.9 NOR Flash on NCS0 27.8.9.1 Hardware Configuration Figure 27-14. NOR Flash on NCS0 D[0..15] A[1..
28. 28.1 Programmable Multibit ECC Controller (PMECC) Description The Programmable Multibit Error Corrected Code Controller (PMECC) is a programmable binary BCH (Bose, Chaudhuri and Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for both SingleLevel Cell (SLC) and Multi-level Cell (MLC) NAND Flash devices. It supports redundancy for correction of 2, 4, 8, 12 or 24 bits of error per sector of data. 28.
28.3 Block Diagram Figure 28-1.
28.4 Functional Description The NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is appended to the page and written in the spare area. This operation is performed by the processor. It moves the content of the PMECCx registers into the NAND Flash memory.
Figure 28-2.
28.4.1 MLC/SLC Write Page Operation using PMECC When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR field of the PMECCFG register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then the SPAREEN bit of the PMECCFG register is set to one. When the NAND spare area contains only redundancy information, the SPAREEN bit is set to zero.
28.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set When the SPAREEN field of the PMECC_CFG register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When the encoding process is over, the redundancy is written to the spare area in user mode, USER field of the PMECC_CTRL must be set to one. Figure 28-3.
28.4.2 MLC/SLC Read Page Operation using PMECC Table 28-3.
28.4.2.2 MLC/SLC Read Operation If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When AUTO field is set to one the ECC is retrieved automatically, otherwise the ECC must be read using user mode. Figure 28-6.
28.5 Software Implementation 28.5.1 Remainder Substitution Procedure The substitute function evaluates the polynomial remainder, with different values of the field primitive elements. The finite field arithmetic addition operation is performed with the Exclusive or. The finite field arithmetic multiplication operation is performed through the gf_log, gf_antilog lookup tables. The REM2NP1 and REMN2NP3 fields of the PMECC_REMx registers contain only odd remainders.
28.5.2 Find the Error Location Polynomial Sigma(x) The sample code below gives a Berlekamp iterative procedure for finding the value of the error location polynomial. The input of the procedure is the si[] table defined in the remainder substitution procedure. The output of the procedure is the error location polynomial named smu (sigma mu). The polynomial coefficients belong to the field. The smu[NB_ERROR+1][] is a table that contains all these coefficients.
/* delta set to 0 */ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; for (i=1; i <= NB_ERROR; i++) { mu[i+1] = i << 1; /*************************************************/ /* */ /* */ /* Compute Sigma (Mu+1) */ /* And L(mu) */ /* check if discrepancy is set to 0 */ if (dmu[i] == 0) { /* copy polynom */ for (j=0; j<2*NB_ERROR_MAX+1; j++) { smu[i+1][j] = smu[i][j]; } /* copy previous polynom order to the next */ lmu[i+1] = lmu[i]; } else { ro = 0; largest = -1; /* find largest delta with dmu != 0 */ for (j=0; j
{ /* galois inverse */ sro[k] = gf_antilog[(gf_log[dmu[i]] + (NB_FIELD_ELEMENTSgf_log[dmu[ro]]) + gf_log[sro[k]]) % NB_FIELD_ELEMENTS]; } } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*NB_ERROR_MAX+1; k++) { smu[i+1][k] = smu[i][k] ^ sro[k]; if (smu[i+1][k]) { /* find the order of the polynom */ lmu[i+1] = k << 1; } } } /* */ /* */ /* End Compute Sigma (Mu+1) */ /* And L(mu) */ /*************************************************/ /* In either case compute delta */ delta[i+1] = (mu[i+1] * 2 - lmu[i+1]
28.6 Programmable Multibit ECC Controller (PMECC) User Interface Table 28-4.
Table 28-4.
28.6.
• AUTO: Automatic Mode Enable This bit is only relevant in NAND Read Mode, when spare enable is activated. 0: Indicates that the spare area is not protected. In that case the ECC computation takes into account the ECC area located in the spare area. (within the start address and the end address). 1: Indicates that the spare is error protected. In this case, the ECC computation takes into account the whole spare area minus the ECC area in the ECC computation operation.
28.6.2 PMECC Spare Area Size Register Name: PMECC_SAREA Address: 0xFFFFE004 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 SPARESIZE 0 SPARESIZE • SPARESIZE: Spare Area Size The spare area size is equal to (SPARESIZE+1) bytes.
28.6.3 PMECC Start Address Register Name: PMECC_SADDR Address: 0xFFFFE008 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 STARTADDR 0 STARTADDR • STARTADDR: ECC Area Start Address (byte oriented address) This field indicates the first byte address of the ECC area. Location 0 matches the first byte of the spare area.
28.6.4 PMECC End Address Register Name: PMECC_EADDR Address: 0xFFFFE00C Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 3 2 1 24 – 16 – 8 ENDADDR 0 ENDADDR • ENDADDR: ECC Area End Address (byte oriented address) This field indicates the last byte address of the ECC area.
28.6.5 PMECC Clock Control Register Name: PMECC_CLK Address: 0xFFFFE010 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 25 – 17 – 9 – 1 CLKCTRL 24 – 16 – 8 – 0 • CLKCTRL: Clock Control Register The PMECC Module data path Setup Time is set to CLKCTRL+1. This field indicates the database setup times in number of clock cycles.
28.6.6 PMECC Control Register Name: PMECC_CTRL Address: 0xFFFFE014 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DISABLE 28 – 20 – 12 – 4 ENABLE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 USER 25 – 17 – 9 – 1 DATA 24 – 16 – 8 – 0 RST • RST: Reset the PMECC Module When set to 1, this bit reset PMECC controller, configuration registers remain unaffected.
28.6.7 PMECC Status Register Name: PMECC_SR Address: 0xFFFFE018 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 ENABLE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 BUSY • BUSY: The Kernel of the PMECC is Busy • ENABLE: PMECC Module Status 0: The PMECC Module is disabled and can be configured. 1: The PMECC Module is enabled and the configuration registers cannot be written.
28.6.
28.6.
28.6.
28.6.11 PMECC Interrupt Status Register Name: PMECC_ISR Address: 0xFFFFE028 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 ERRIS • ERRIS: Error Interrupt Status Register When set to one, bit i of the PMECCISR register indicates that sector i is corrupted.
28.6.12 PMECC ECC x Register Name: PMECC_ECCx [x=0..10] [sec_num=0..7] Addresses: 0xFFFFE040 [0][0] .. 0xFFFFE068 [10][0] 0xFFFFE080 [0][1] .. 0xFFFFE0A8 [10][1] 0xFFFFE0C0 [0][2] .. 0xFFFFE0E8 [10][2] 0xFFFFE100 [0][3] .. 0xFFFFE128 [10][3] 0xFFFFE140 [0][4] .. 0xFFFFE168 [10][4] 0xFFFFE180 [0][5] .. 0xFFFFE1A8 [10][5] 0xFFFFE1C0 [0][6] .. 0xFFFFE1E8 [10][6] 0xFFFFE200 [0][7] ..
28.6.13 PMECC Remainder x Register Name: PMECC_REMx [x=0..11] [sec_num=0..7] Addresses: 0xFFFFE240 [0][0] .. 0xFFFFE26C [11][0] 0xFFFFE280 [0][1] .. 0xFFFFE2AC [11][1] 0xFFFFE2C0 [0][2] .. 0xFFFFE2EC [11][2] 0xFFFFE300 [0][3] .. 0xFFFFE32C [11][3] 0xFFFFE340 [0][4] .. 0xFFFFE36C [11][4] 0xFFFFE380 [0][5] .. 0xFFFFE3AC [11][5] 0xFFFFE3C0 [0][6] .. 0xFFFFE3EC [11][6] 0xFFFFE400 [0][7] ..
29. Programmable Multibit ECC Error Location Controller (PMERRLOC) 29.1 Description The PMECC Error Location Controller (PMERRLOC) provides hardware acceleration for determining roots of polynomials over two finite fields: GF(2^13) and GF(2^14). It integrates 24 fully programmable coefficients. These coefficients belong to GF(2^13) or GF(2^14). The coefficient programmed in the PMERRLOC_SIGMAx register is the coefficient of degree x in the polynomial. 29.2 29.
29.4 Functional Description The PMERRLOC search operation is started as soon as a write access is detected in the ELEN register and can be disabled by writing to the ELDIS register. The ENINIT field of the ELEN register shall be initialized with the number of Galois field elements to test. The set of the roots can be limited to a valid range. Table 29-1. ENINIT field value for a sector size of 512 bytes Error Correcting Capability ENINIT Value 2 4122 4 4148 8 4200 12 4252 24 4408 Table 29-2.
29.5 Programmable Multibit ECC Error Location (PMERRLOC) User Interface Table 29-3.
29.5.1 Error Location Configuration Register Name: PMERRLOC_ELCFG Address: 0xFFFFE600 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 27 – 19 12 – 4 – 11 – 3 – 26 – 18 ERRNUM 10 – 2 – 25 – 17 24 – 16 9 – 1 – 8 – 0 SECTORSZ • ERRNUM: Number of Errors • SECTORSZ: Sector Size 0: The ECC computation is based on a 512-byte sector. 1: The ECC computation is based on a 1024-byte sector.
29.5.
29.5.
29.5.
29.5.
29.5.
29.5.
29.5.
29.5.
29.5.10 Error Location SIGMAx Register Name: PMERRLOC_SIGMAx [x=0..24] Address: 0xFFFFE628 [0] .. 0xFFFFE688 [24] Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 5 4 3 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 SIGMAx SIGMAx • SIGMAx: Coefficient of Degree x in the SIGMA Polynomial. SIGMAx belongs to the finite field GF(2^13) when the sector size is set to 512 bytes.
29.5.11 PMECC Error Locationx Register Name: PMERRLOC_ELx [x=0..23] Address: 0xFFFFE68C Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 5 4 3 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 ERRLOCN ERRLOCN • ERRLOCN: Error Position within the Set {sector area, spare area}. ERRLOCN points to 0 when the first bit of the main area is corrupted.
30. Static Memory Controller (SMC) 30.1 Description The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
30.3 I/O Lines Description Table 30-1.
30.5 Application Example 30.5.1 Hardware Interface Figure 30-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 D0 - D7 128K x 8 SRAM D8-D15 D0 - D7 CS NWR0/NWE A2 - A25 A2 - A18 A0 - A16 NRD OE NWR1/NBS1 WE 128K x 8 SRAM D16 - D23 D24-D31 D0 - D7 A0 - A16 NRD Static Memory Controller 30.
30.7 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 30-2).
30.8.2 Byte Write or Byte Select Access Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. Figure 30-3. Memory Connection for an 8-bit Data Bus D[7:0] D[7:0] A[18:2] A[18:2] SMC A0 A0 A1 A1 NWE Write Enable NRD Output Enable NCS[2] Memory Enable Figure 30-4.
30.8.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
30.8.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 30-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused.
30.9 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 30.9.
30.9.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
30.9.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation. 30.9.2.
30.9.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 30-11 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be.
30.9.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 30-12. The write cycle starts with the address setting on the memory address bus. 30.9.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3.
30.9.3.3 Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles.
30.9.4 Write Mode The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal controls the write operation. 30.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1) Figure 30-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal.
30.9.5 Write Protected Registers To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write protected by setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR). If a write access in a write protected register is detected, then the WPVS flag in the SMC Write Protect Status Register (SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See Section 30.10.2 ”Early Read Wait State”. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus.
30.10.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).
Figure 30-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD no hold no setup D[31:0] write cycle (WRITE_MODE = 0) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) Figure 30-19.
30.10.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State.
30.11 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: before starting a read access to a different external memory before starting a write access to the same device or to a different external one. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select.
Figure 30-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS tpacc D[31:0] TDF = 3 clock cycles NCS controlled read operation 30.11.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
Figure 30-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK A[25:2] NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[31:0] read access on NCS0 (NRD controlled) Read to Write Wait State write access on NCS0 (NWE controlled) 30.11.3 TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins.
Figure 30-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[31:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 30-24.
Figure 30-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[31:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 30.12 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
30.12.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 30-26.
Figure 30-27.
30.12.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 30-28 and Figure 30-29. After deassertion, the access is completed: the hold step of the access is performed.
Figure 30-29.
30.12.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
30.13 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
30.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 30-32. The external device may not be fast enough to support such timings. Figure 30-33 illustrates the recommended procedure to properly switch from one mode to the other. Figure 30-32.
30.14 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
In page mode, the programming of the read timings is described in Table 30-7: Table 30-7. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
Figure 30-35.
30.15 Programmable IO Delays The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, SMC_DELAY1-8. The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT).
30.16 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 30-8. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 30-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 30-8.
30.16.1 SMC Setup Register Name: SMC_SETUP[0..
30.16.2 SMC Pulse Register Name: SMC_PULSE[0..
30.16.3 SMC Cycle Register Name: SMC_CYCLE[0..5] Addresses: 0xFFFFEA08 [0], 0xFFFFEA18 [1], 0xFFFFEA28 [2], 0xFFFFEA38 [3], 0xFFFFEA48 [4], 0xFFFFEA58 [5] Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – NRD_CYCLE 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 – – – – – – – NWE_CYCLE 7 6 5 4 3 2 1 0 NWE_CYCLE • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
30.16.4 SMC MODE Register Name: SMC_MODE[0..5] Addresses: 0xFFFFEA0C [0], 0xFFFFEA1C [1], 0xFFFFEA2C [2], 0xFFFFEA3C [3], 0xFFFFEA4C [4], 0xFFFFEA5C [5] Access: Read-write 31 30 – – 23 22 21 20 – – – TDF_MODE 15 14 13 12 – – 7 6 – – 29 28 PS DBW 5 4 EXNW_MODE 27 26 25 24 – – – PMEN 19 18 17 16 TDF_CYCLES 11 10 9 8 – – – BAT 3 2 1 0 – – WRITE_MODE READ_MODE • READ_MODE: 1: The read operation is controlled by the NRD signal.
• BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
30.16.5 SMC DELAY I/O Register Name: SMC_DELAY 1-8 Addresses: 0xFFFFEAC0 [1] .. 0xFFFFEADC [8] Access: Read-write Reset: See Table 30-8 31 30 29 28 27 26 Delay8 23 22 21 20 19 18 Delay6 15 14 13 6 24 17 16 9 8 1 0 Delay5 12 11 10 Delay4 7 25 Delay7 Delay3 5 Delay2 4 3 2 Delay1 • Delay x: Gives the number of elements in the delay line.
30.16.6 SMC Write Protect Mode Register Name: SMC_WPMR Address: 0xFFFFEAE4 Access: Read-write Reset: See Table 30-8 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
30.16.7 SMC Write Protect Status Register Name: SMC_WPSR Address: 0xFFFFEAE8 Access: Read-only Reset: See Table 30-8 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register.
31. DDR SDR SDRAM Controller (DDRSDRC) 31.1 Description The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol. The DDRSDRC extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRSDRAM device and external 16-bit DDR-SDRAM device.
31.
31.3 DDRSDRC Module Diagram Figure 31-1.
31.4 Initialization Sequence The addresses given are for example purposes only. The real address depends on implementation in the product. 31.4.1 SDR-SDRAM Initialization The initialization sequence is generated by software. The SDR-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 31.7.8 on page 455). 2. Program the features of the SDR-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.
31.4.2 Low-power DDR1-SDRAM Initialization The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 31.7.8 on page 455). 2. Program the features of the low-power DDR1-SDRAM device into the Configuration Register: asynchronous timing (trc, tras, etc.), number of columns, rows, banks, cas latency. See Section 31.7.3 on page 446, Section 31.7.
31.4.3 DDR2-SDRAM Initialization The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 31.7.8 on page 455). 2. Program the features of DDR2-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows, banks, cas latency and output drive strength) (see Section 31.7.
14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The application must set Mode to 3 in the Mode Register (see Section 31.7.1 on page 444) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1:0] are set to 0.
31.5 Functional Description 31.5.1 SDRAM Controller Write Cycle The DDRSDRC allows burst access or single access in normal mode (mode = 0). Whatever the access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance. The SDRAM device is programmed with a burst length equal to 8. This determines the length of a sequential data input by the write command that is set to 8. The latency from write command to data input is fixed to 1 in the case of DDRSDRAM devices.
Figure 31-2. Single Write Access, Row Closed, Low-power DDR1-SDRAM Device SDCLK Row a A[12:0] COMMAND BA[1:0] PRCHG NOP NOP col a ACT NOP WRITE NOP 00 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da Trp = 2 3 Db Trcd = 2 Figure 31-3.
Figure 31-4. Single Write Access, Row Closed, SDR-SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] Row a NOP PRCHG NOP ACT Col a NOP WRITE BST NOP 00 3 DM[1:0] 0 D[31:0] 3 DaDb Trp = 2 Trcd = 2 Figure 31-5.
Figure 31-6. Burst Write Access, Row Closed, DDR2-SDRAM Device SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da Db Dc Dd 3 De Df Dg Dh Trcd = 2 Trp = 2 Figure 31-7.
Figure 31-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM Device SDCLK A[12:0] col a COMMAND NOP BA[1:0] col a WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] 3 0 D[15:0] 3 Da Db Dc Dd De Df Dg Dh Da Db Twrd = BL/2 +2 = 8/2 +2 = 6 Twr = 1 In the case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle prior to the read command to avoid writing invalid data.
Figure 31-10. SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] col a Row a NOP PRCHG NOP ACT NOP WRITE NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da 3 Da Db Db Data masked twtr 31.5.2 SDRAM Controller Read Cycle The DDRSDRC allows burst access or single access in normal mode (mode = 0). Whatever access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps within these 8 columns if the boundary is reached. These 8 columns are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block.
Figure 31-12. Single Read Access, Row Close, Latency = 3, DDR2-SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] NOP PRCHG NOP Row a Col a ACT NOP READ 0 DQS[1] DQS[0] DM[1:0] 3 D[15:0] Da Trp Db Latency = 2 Trcd Figure 31-13.
Figure 31-14. Burst Read Access, Latency = 2, Low-power DDR1-SDRAM Devices SDCLK Col a A[12:0] COMMAND BA[1:0] NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Dc Dd De Db Dc Df Dg Dh Latency = 2 Figure 31-15.
Figure 31-16. Burst Read Access, Latency = 2, SDR-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] col a NOP READ NOP BST NOP 0 DQS[1:0] DM[3:0] F D[31:0] DaDb DcDd DeDf Dg Dh Latency = 2 31.5.3 Refresh (Auto-refresh Command) An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these auto-refresh commands periodically.
PASR/DS/TCR bits are updated before entry into self-refresh mode if DDRSDRC does not share an external bus with another controller or during a refresh command, and a pending read or write access, if DDRSDRC does share an external bus with another controller. This type of update is a function of the UPD_MR bit (see Section 31.7.7 “DDRSDRC Low-power Register” on page 453).
Figure 31-19. Self-refresh Mode Exit SDCLK A[12:0] COMMAND NOP VALID NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] DaDb Exit Self Refresh mode clock must be stable before exiting self refresh mode TXNRD/TXSRD TXSR TXSR (DDR device) (Low-power DDR1 device) (Low-power SDR, SDR-SDRAM device) Figure 31-20.
Figure 31-21. Automatic Update During AUTO-REFRESH Command and SDRAM Access SDCLK A[12:0] COMMAND Pasr-Tcr-Ds NOP PRCHALL NOP ARFSH NOP MRS NOP ACT CKE BA[1:0] 0 0 2 Trp Trfc Tmrd Update Extended mode register 31.5.4.2 Power-down Mode This mode is activated by setting the low-power command bits (LPCB) to ‘2’ in “DDRSDRC Low-power Register” . Power-down mode is used when no access to the SDRAM device is possible. In this mode, power consumption is greater than in self-refresh mode.
Figure 31-22. Power-down Entry/Exit, Timeout = 0 SDCLK A[12:0] COMMAND READ BST NOP READ CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Exit power down mode Entry power down mode 31.5.4.3 Deep Power-down Mode The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal voltage generators inside the device are stopped and all data is lost. This mode is activated by setting the low-power command bit (LPCB) to ‘3’ in “DDRSDRC Low-power Register” .
31.5.4.4 Reset Mode The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-power command bit (LPCB) to ‘3’ and the clock frozen command bit (CLK_FR) to ‘1’ in “DDRSDRC Low-power Register” . When this mode is enabled, the DDRSDRC leaves normal mode (mode = 0) and the controller is frozen. Before enabling this mode, the end user must assume there is not an access in progress.
The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the SDRAM device at the same time. The arbitration type is round-robin arbitration. This algorithm dispatches the requests from different masters to the SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is serviced first, then the others are serviced in a round-robin manner.
31.5.6 Write Protected Registers To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be writeprotected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
31.6 Software Interface/SDRAM Organization, Address Mapping The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps different memory types depending on the values set in the DDRSDRC Configuration Register. See Section 31.7.3 “DDRSDRC Configuration Register” on page 446. The following figures illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths.
Table 31-4. Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 17 16 15 14 13 12 11 10 9 8 7 Row[13:0] Bk[1:0] 5 4 3 2 1 M0 Column[9:0] Row[13:0] 0 M0 Column[8:0] Row[13:0] Bk[1:0] 6 M0 Column[10:0] Table 31-5.
Table 31-8. Interleaved Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[13:0] 11 10 9 8 7 Bk[1:0] Row[13:0] 5 4 3 2 1 M0 Column[9:0] Bk[1:0] 0 M0 Column[8:0] Bk[1:0] Row[13:0] 6 M0 Column[10:0] 31.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks Table 31-9.
Table 31-14. SDR-SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 7 Row[11:0] Bk[1:0] 4 3 2 0 M[1:0] Column[9:0] Row[11:0] 1 M[1:0] Column[8:0] Row[11:0] Bk[1:0] 5 Column[7:0] Row[11:0] Bk[1:0] 6 M[1:0] Column[10:0] M[1:0] Table 31-15.
31.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface The User Interface is connected to the APB bus. The DDRSDRC is programmed using the registers listed in Table 31-16 Table 31-16.
31.7.1 DDRSDRC Mode Register Name: DDRSDRC_MR Address: 0xFFFFE800 Access: Read-write Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – MODE This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” .
31.7.2 DDRSDRC Refresh Timer Register Name: DDRSDRC_RTR Address: 0xFFFFE804 Access: Read-write Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – 7 6 5 4 1 0 COUNT 3 2 COUNT This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” .
31.7.3 DDRSDRC Configuration Register Name: DDRSDRC_CR Address: 0xFFFFE808 Access: Read-write Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – DECOD – NB – ACTBST – EBISHARE 15 14 13 12 11 10 9 8 – – DIS_DLL DIC 2 1 – OCD 7 6 DLL 5 4 3 CAS NR 0 NC This register can only be written if the if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” .
• CAS: CAS Latency The reset value is 2 cycles. CAS DDR2 CAS Latency SDR CAS Latency 0 Reserved Reserved 1 Reserved Reserved 2 Reserved 2 3 3 3 4 Reserved Reserved 5 Reserved Reserved 6 Reserved Reserved 7 Reserved Reserved • DLL: Reset DLL Reset value is 0. This field defines the value of Reset DLL. 0: Disable DLL reset. 1: Enable DLL reset. This value is used during the power-up sequence. Note: This field is found only in DDR2-SDRAM devices.
• EBISHARE: External Bus Interface is Shared The DDR controller embedded in the EBI is used at the same time as another memory controller (SMC,..) Reset value is 0. 0: Only the DDR controller function is used. 1: The DDR controller shares the EBI with another memory controller (SMC, NAND,..) • ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y Reset value is 0. 0: After an ACTIVE command in Bank X, BURST STOP command can be issued to another bank to stop current read access.
31.7.4 DDRSDRC Timing Parameter 0 Register Name: DDRSDRC_TPR0 Address: 0xFFFFE80C Access: Read-write Reset: See Table 31-16 31 30 29 28 TMRD 23 22 27 26 21 20 19 14 18 13 6 17 16 9 8 1 0 TRP 12 11 10 TRC 7 24 TWTR TRRD 15 25 REDUCE_WRRD TWR 5 TRCD 4 3 2 TRAS This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” . • TRAS: Active to Precharge Delay Reset Value is 5 cycles.
• TWTR: Internal Write to Read Delay Reset value is 0. This field is relevant only for Low-power DDR1-SDRAM devices and DDR2-SDRAM devices. This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7.
31.7.5 DDRSDRC Timing Parameter 1 Register Name: DDRSDRC_TPR1 Address: 0xFFFFE810 Access: Read-write Reset: See Table 31-16 31 30 29 28 – – – – 23 22 21 20 27 26 25 24 TXP 19 18 17 16 11 10 9 8 2 1 0 TXSRD 15 14 13 12 TXSNR 7 6 5 – – – 4 3 TRFC This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” . • TRFC: Row Cycle Delay Reset Value is 8 cycles.
31.7.6 DDRSDRC Timing Parameter 2 Register Name: DDRSDRC_TPR2 Address: 0xFFFFE814 Access: Read-write Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 9 8 1 0 TFAW 11 10 TRTP 7 6 5 TRPA 4 3 2 TXARDS TXARD This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” . • TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
31.7.7 DDRSDRC Low-power Register Name: DDRSDRC_LPR Address: 0xFFFFE81C Access: Read-write Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – APDE 15 14 11 10 9 8 – – 7 6 – UPD_MR 13 12 TIMEOUT 5 – 4 3 PASR DS 2 1 CLK_FR 0 LPCB • LPCB: Low-power Command Bit Reset value is 0.
After the initialization sequence, as soon as PASR field is modified, Extended Mode Register in the external device memory is accessed automatically and PASR bits are updated. In function of the UPD_MR bit, update is done before entering in self-refresh mode or during a refresh command and a pending read or write access. • DS: Drive Strength Reset value is “0”. Note: This field is unique to Low-power SDRAM. It selects the driver strength of SDRAM output (see memory devices datasheet for details).
31.7.8 DDRSDRC Memory Device Register Name: DDRSDRC_MD Address: 0xFFFFE820 Access: Read-write Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – DBW – MD This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” . • MD: Memory Device Indicates the type of memory used.
31.7.9 DDRSDRC DLL Register Name: DDRSDRC_DLL Address: 0xFFFFE824 Access: Read-only Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 MDVAL 7 6 5 4 3 2 1 0 – – – – – MDOVF MDDEC MDINC The DLL logic is internally used by the controller in order to delay DQS inputs. This is necessary to center the strobe time and the data valid window.
31.7.10 DDRSDRC High Speed Register Name: DDRSDRC_HS Address: 0xFFFFE82C Access: Read-write Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – DIS_ANTICIP_RE AD – – – – – – This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” .
31.7.11 DDRSDRC Write Protect Mode Register Name: DDRSDRC_WPMR Address: 0xFFFFE8E4 Access: Read-write Reset: See Table 31-16 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
31.7.12 DDRSDRC Write Protect Status Register Name: DDRSDRC_WPSR Address: 0xFFFFE8E8 Access: Read-only Reset: See Table 31-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR register.
32. DMA Controller (DMAC) 32.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer.
32.3 DMA Controller Peripheral Connections The DMA Controller handles the transfer between peripherals and memory and receives triggers from the peripherals listed in table that follows. For each listed DMA Channel Number, the SIF and/or DIF bitfields in the DMAC_CTRLBx register must be programmed with a value compatible to the MATRIX “Master to Slave Access” definition provided in the “Bus Matrix (MATRIX)” section of the product datasheet. See Section 32.8.17 ”DMAC Channel x [x = 0..
32.4 Block Diagram Figure 32-1.
32.5 Functional Description 32.5.1 Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
Figure 32-2. DMAC Transfer Hierarchy for Non-Memory Peripheral DMAC Transfer Buffer Buffer Chunk Transfer AMBA Burst Transfer DMA Transfer Level Buffer Transfer Level Buffer Chunk Transfer Chunk Transfer AMBA Single Transfer AMBA Burst Transfer AMBA Burst Transfer Single Transfer DMA Transaction Level AMBA Single Transfer AMBA Transfer Level Figure 32-3.
Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The source and destination can independently select which method to use. Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the next linked list item (LLI) exists.
32.5.2 Memory Peripherals Figure 32-3 on page 464 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled.
32.5.4 DMAC Transfer Types A DMAC transfer may consist of single or multi-buffer transfers.
Figure 32-5.
32.5.4.2 Programming DMAC for Multiple Buffer Transfers Table 32-2.
Suspension of Transfers Between Buffers At the end of every buffer transfer, an end of buffer interrupt is asserted if: Note: the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number. The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the destination.
6. Write the channel configuration information into the DMAC_CFGx register for channel x. i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. ii.
4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are set as shown in Row 4 of Table 32-2 on page 469. The LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in Row 1 of Table 32-2. Figure 32-5 on page 468 shows a Linked List example with two list items. 5. Make sure that the LLI.
Figure 32-7. Multi-buffer with Linked List Address for Source and Destination Address of Destination Layer Address of Source Layer Buffer 2 SADDR(2) Buffer 2 DADDR(2) Buffer 1 SADDR(1) Buffer 1 DADDR(1) Buffer 0 Buffer 0 DADDR(0) SADDR(0) Source Buffers Destination Buffers If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.
Figure 32-9 presents the DMAC transfer flow. Figure 32-9.
Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10) 1. Read the Channel Handler Status register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. Program the following channel registers: 1. Write the starting source address in the DMAC_SADDRx register for channel x. 2.
6. The DMAC transfer proceeds as follows: 1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed. It then stalls until the STALx bit of DMAC_CHSR register is cleared by software, writing ‘1’ to DMAC_CHER.KEEPx bit, where x is the channel number.
Figure 32-11.
4. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
18. The DMAC reloads the DMAC_SADDRx register from the initial value. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC samples the row number as shown in Table 32-2 on page 469. If the DMAC is in Row 1, then the DMAC transfer has completed. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. You can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Enable. (DMAC_CHSR.
Figure 32-13.
Incrementing/decrementing or fixed address for source in SRC_INCR field. Incrementing/decrementing or fixed address for destination in DST_INCR field. 5. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 6. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. 7. Write the channel configuration information into the DMAC_CFGx register for channel x. i.
Figure 32-14.
Figure 32-15.
Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Set up the linked list in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: 3. Note: 4. 1.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx registers are fetched. The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The DMAC_DADDRx register in the DMAC remains unchanged. 16. Source and destination requests single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals).
Figure 32-17 presents the DMAC transfer flow. Figure 32-17.
32.5.6 Disabling a Channel Prior to Transfer Completion Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register, DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register. 1.
32.6 DMAC Software Requirements There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel. You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte, half-word and word aligned address depending on the source width and destination width.
32.7 Write Protection Registers To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be write protected by setting the WPEN bit in the “DMAC Write Protect Mode Register” (DMAC_WPMR). If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect Status Register (MCI_WPSR) is set, and the WPVSRC field indicates in which register the write access has been attempted.
32.8 DMA Controller (DMAC) User Interface Table 32-4.
32.8.1 DMAC Global Configuration Register Name: DMAC_GCFG Address: 0xFFFFEC00 Access: Read-write Reset: 0x00000010 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 DICEN 7 – 6 – 5 – 4 ARB_CFG 3 – 2 – 1 – 0 – Note: Bit fields 0, 1, 2, and 3 have a default value of 0. This should not be changed. This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
32.8.2 DMAC Enable Register Name: DMAC_EN Address: 0xFFFFEC04 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENABLE This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” . • ENABLE: General Enable of DMA 0: DMA Controller is disabled. 1: DMA Controller is enabled.
32.8.3 DMAC Software Single Request Register Name: DMAC_SREQ Address: 0xFFFFEC08 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DSREQ7 14 SSREQ7 13 DSREQ6 12 SSREQ6 11 DSREQ5 10 SSREQ5 9 DSREQ4 8 SSREQ4 7 DSREQ3 6 SSREQ3 5 DSREQ2 4 SSREQ2 3 DSREQ1 2 SSREQ1 1 DSREQ0 0 SSREQ0 • DSREQx: Destination Request Request a destination single transfer on channel i.
32.8.4 DMAC Software Chunk Transfer Request Register Name: DMAC_CREQ Address: 0xFFFFEC0C Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DCREQ7 14 SCREQ7 13 DCREQ6 12 SCREQ6 11 DCREQ5 10 SCREQ5 9 DCREQ4 8 SCREQ4 7 DCREQ3 6 SCREQ3 5 DCREQ2 4 SCREQ2 3 DCREQ1 2 SCREQ1 1 DCREQ0 0 SCREQ0 • DCREQx: Destination Chunk Request Request a destination chunk transfer on channel i.
32.8.
32.8.
32.8.
32.8.
32.8.
32.8.10 DMAC Channel Handler Enable Register Name: DMAC_CHER Address: 0xFFFFEC28 Access: Write-only Reset: 0x00000000 31 KEEP7 30 KEEP6 29 KEEP5 28 KEEP4 27 KEEP3 26 KEEP2 25 KEEP1 24 KEEP0 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SUSP7 14 SUSP6 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 ENA7 6 ENA6 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 • ENAx: Enable [7:0] When set, a bit of the ENA field enables the relevant channel.
32.8.11 DMAC Channel Handler Disable Register Name: DMAC_CHDR Address: 0xFFFFEC2C Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RES7 14 RES6 13 RES5 12 RES4 11 RES3 10 RES2 9 RES1 8 RES0 7 DIS7 6 DIS6 5 DIS5 4 DIS4 3 DIS3 2 DIS2 1 DIS1 0 DIS0 • DISx: Disable [7:0] Write one to this field to disable the relevant DMAC Channel.
32.8.
32.8.13 DMAC Channel x [x = 0..7] Source Address Register Name: DMAC_SADDRx [x = 0..7] Addresses: 0xFFFFEC3C [0], 0xFFFFEC64 [1], 0xFFFFEC8C [2], 0xFFFFECB4 [3], 0xFFFFECDC [4], 0xFFFFED04 [5], 0xFFFFED2C [6], 0xFFFFED54 [7] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SADDR 23 22 21 20 SADDR 15 14 13 12 SADDR 7 6 5 4 SADDR This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
32.8.14 DMAC Channel x [x = 0..7] Destination Address Register Name: DMAC_DADDRx [x = 0..
32.8.15 DMAC Channel x [x = 0..7] Descriptor Address Register Name: DMAC_DSCRx [x = 0..
32.8.16 DMAC Channel x [x = 0..7] Control A Register Name: DMAC_CTRLAx [x = 0..
Value Name Description 101 CHK_64 64 data transferred 110 CHK_128 128 data transferred 111 CHK_256 256 data transferred • SRC_WIDTH: Transfer Width for the Source Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfer size is set to 16-bit width 1X WORD the transfer size is set to 32-bit width • DST_WIDTH: Transfer Width for the Destination Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfe
32.8.17 DMAC Channel x [x = 0..7] Control B Register Name: DMAC_CTRLBx [x = 0..
• DST_DSCR: Destination Address Descriptor 0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination. • FC: Flow Control This field defines which device controls the size of the buffer transfer, also referred to as the Flow Controller.
32.8.18 DMAC Channel x [x = 0..7] Configuration Register Name: DMAC_CFGx [x = 0..
• DST_PER_MSB: DST_PER Most Significant Bits This field indicates the Most Significant bits of the DST_PER field. • SOD: Stop On Done 0 (DISABLE): STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 (ENABLE): STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
32.8.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register Name: DMAC_SPIPx [x = 0..
32.8.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register Name: DMAC_DPIPx [x = 0..
32.8.21 DMAC Write Protect Mode Register Name: DMAC_WPMR Address: 0xFFFFEDE4 Access: Read-write Reset: See Table 32-4 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII).
32.8.22 DMAC Write Protect Status Register Name: DMAC_WPSR Address: 0xFFFFEDE8 Access: Read-only Reset: See Table 32-4 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the DMAC_WPSR register.
33. USB Device Port (UDP) 33.1 Description The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
33.3 Block Diagram Figure 33-1. Block Diagram Atmel Bridge MCK USB Device APB to MCU Bus txoen U s e r I n t e r f a c e UDPCK udp_int W r a p p e r Dual Port RAM FIFO W r a p p e r eopn Serial Interface Engine 12 MHz txd rxdm Embedded USB Transceiver DDP DDM rxd SIE rxdp Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers.
33.4 Product Dependencies For further details on the USB Device hardware implementation, see the specific Product Properties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM are available from the product boundary. 33.4.1 I/O Lines DDP and DDM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB device peripheral.
33.5 Typical Connection Figure 33-2. Board Schematic to Interface Device Peripheral PIO 5V Bus Monitoring 27 K 47 K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 33.5.1 USB Device Transceiver The USB device transceiver is embedded in the product. A few discrete components are required as follows: the application detects all device states as defined in chapter 9 of the USB specification; VBUS monitoring to reduce power consumption the host is disconnected for line termination. 33.5.
33.6 Functional Description 33.6.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 33-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.
33.6.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 33-5.
Figure 33-4. Control Read and Write Sequences Setup Stage Control Read Setup TX Setup Stage Control Write No Data Control Setup TX Data Stage Data OUT TX Status Stage Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Data IN TX Status IN TX Status Stage Status OUT TX Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID.
33.6.2 Handling Transactions with USB V2.0 Device Peripheral 33.6.2.1 Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments.
4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 6.
Figure 33-7.
Figure 33-8.
Figure 33-9.
3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 6.
33.6.2.4 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) To abort the current request, a protocol stall is used, but uniquely with control transfer.
33.6.2.5 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability refer to Table 33-1 ”USB Endpoint Description”. Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.
33.6.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 33-14.
33.6.3.2 Entering Attached State To enable integrated pull-up, the PUON bit in the UDP_TXVC register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pull-up connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled. 33.6.3.
33.6.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pull-up shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks.
33.7 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Table 33-6.
33.7.1 UDP Frame Number Register Name: UDP_FRM_NUM Address: 0xF803C000 Access: Read-only 31 --- 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
33.7.2 UDP Global State Register Name: UDP_GLB_STAT Address: 0xF803C004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 RMWUPE 3 RSMINPR 2 ESR 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state.
33.7.3 UDP Function Address Register Name: UDP_FADDR Address: 0xF803C008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
33.7.
33.7.
33.7.
33.7.
• SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence.
33.7.8 UDP Interrupt Clear Register Name: UDP_ICR Address: 0xF803C020 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 EXTRSM 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt.
33.7.
33.7.10 UDP Endpoint Control and Status Register (Control, Bulk Interrupt Endpoints) Name: UDP_CSRx [x = 0..
/// Clears the specified bit(s) in the UDP_CSR register. /// \param endpoint The endpoint number of the CSR to process. /// \param flags The bitmap to clear to 0.
• RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device.
• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
Value Name Description 010 BULK_OUT Bulk OUT 110 BULK_IN Bulk IN 011 INT_OUT Interrupt OUT 111 INT_IN Interrupt IN • DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. • EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint.
33.7.11 UDP Endpoint Control and Status Register (Isochronous Endpoints) Name: UDP_CSRx [x = 0..
Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware.
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO’s Bank 1. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1.
• EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero). • RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller.
33.7.12 UDP FIFO Data Register Name: UDP_FDRx [x = 0..5] Address: 0xF803C050 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host).
33.7.13 UDP Transceiver Control Register Name: UDP_TXVC Address: 0xF803C074 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 PUON TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.
34. USB Host Port (UHP) 34.1 Description The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed halfduplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.
34.3 Block Diagram Figure 34-1. Block Diagram HCI Slave Block AHB Slave OHCI Registers OHCI Root Hub Registers List Processor Block Control ED & TD Regsisters Root Hub and Host SIE Embedded USB v2.0 Full-speed Transceiver PORT S/M USB transceiver DP DM PORT S/M USB transceiver DP DM AHB HCI Master Block Data FIFO 64 x 8 Master uhp_int MCK UHPCK Access to the USB host operational registers is achieved through the AHB bus slave interface.
34.4 Product Dependencies 34.4.1 I/O Lines DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host controller. 34.4.2 Power Management The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%.
34.5 Functional Description Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a. 34.5.1 Host Controller Interface There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The operational registers contain control, status and list pointer registers.
34.5.2 Host Controller Driver Figure 34-3. USB Host Drivers User Application User Space Kernel Drivers Mini Driver Class Driver Class Driver HUB Driver USB Driver Host Controller Driver Hardware Host Controller Hardware USB Handling is done through several layers as follows: 34.6 Host controller hardware and serial engine: Transmits and receives USB data on the bus. Host controller driver: Drives the Host controller hardware and handles the USB protocol.
35. High Speed MultiMedia Card Interface (HSMCI) 35.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
35.3 Block Diagram Figure 35-1. Block Diagram (8-bit Configuration) APB Bridge DMAC APB MCCK (1) MCCDA HSMCI Interface PMC MCK (1) MCDA0 (1) PIO MCDA1 (1) MCDA2 (1) MCDA3 (1) MCDA4 (1) MCDA5 (1) Interrupt Control MCDA6 (1) MCDA7 (1) HSMCI Interrupt Note: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy.
35.4 Application Block Diagram Figure 35-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 10 11 1213 8 SDCard MMC 35.5 Pin Name List Table 35-1. I/O Lines Description for 8-bit Configuration Pin Name(1) Pin Description Type(2) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA7 Data 0..
35.6 Product Dependencies 35.6.1 I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 35-2.
The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 35-4.
Figure 35-5. SD Memory Card Bus Topology 1 2 3 4 56 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 35-5. Table 35-5.
35.8 High Speed MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus protocol. Each message is represented by one of the following tokens: Command—A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in Table 35-6 and Table 357. Table 35-6. ALL_SEND_CID Command Description CMD Index Type Argument Response Abbreviation Command Description CMD2 bcr(1) [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note: 1. bcr means broadcast command with response. Table 35-7.
Figure 35-7. Command/Response Functional Flow Diagram Set the command argument HSMCI_ARGR = Argument(1) Set the command HSMCI_CMDR = Command Read HSMCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? RETURN ERROR(1) Read response if required Does the command involve a busy indication? No RETURN OK Read HSMCI_SR 0 NOTBUSY 1 RETURN OK Note: 1.
35.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the DMA Controller. In all cases, the block length (BLKLEN field) must be defined either in the Mode Register (HSMCI_MR), or in the Block Register (HSMCI_BLKR).
35.8.3 Read Operation The following flowchart (Figure 35-8) shows how to read a single block with or without use of DMAC facilities. In this example, a polling method is used to wait for the end of read. Similarly, the user can configure the Interrupt Enable Register (HSMCI_IER) to trigger an interrupt at the end of read. Figure 35-8.
35.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer. The following flowchart (Figure 35-9) shows how to write a single block with or without use of DMA facilities.
Figure 35-9.
The following flowchart (Figure 35-10) shows how to manage read multiple block and write multiple block transfers with the DMA Controller. Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (HSMCI_IMR). Figure 35-10.
35.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller 1. Wait until the current command execution has successfully terminated. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI Configuration Register with block_length value. 4. Configure the fields of the HSMCI_DMA register as follows: 3. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR OFFSET field with dma_offset.
35.8.6 READ_SINGLE_BLOCK Operation using DMA Controller 35.8.6.1 Block Length is Multiple of 4 1. Wait until the current command execution has successfully completed. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI Configuration Register with block_length value. 4. Set RDPROOF bit in HSMCI_MR to avoid overflow. 5. Configure the fields of the HSMCI_DMA register as follows: 1.
35.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0) In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to copy exactly the block length number of bytes using 2 transfer descriptors. 1. Use the previous step until READ_SINGLE_BLOCK then 2.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). 14. Configure the fields of LLI_B.DMAC_CTRLBx as follows: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0. –DIF and SIF are set with their respective layer ID.
–Both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled) –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously. 8. Configure the fields of DMAC_CFGx for Channel x as follows: –FIFOCFG defines the watermark of the DMA channel FIFO. –SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–Both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able to prefetch data and write HSMCI simultaneously. 8. Configure the fields of LLI(n).DMAC_CFGx for Channel x as follows: –FIFOCFG defines the watermark of the DMA channel FIFO. –DST_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_REP is set to 0.
6. Configure the fields of LLI_W(n).DMAC_CTRLAx as follows: –DST_WIDTH is set to WORD –SRC_WIDTH is set to WORD –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length/4. 7. Configure the fields of LLI_W(n).DMAC_CTRLBx as follows: –DST_INCR is set to INCR. –SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
6. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned. 7. Configure the fields of LLI_W(n).DMAC_CTRLAx as follows: –DST_WIDTH is set to WORD. –SRC_WIDTH is set to WORD. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is skipped later. 8. Configure the fields of LLI_W(n).DMAC_CTRLBx as follows: –DST_INCR is set to INCR. –SRC_INCR is set to INCR.
16. Configure the LLI_B(n).DMAC_CFGx memory location for Channel x as follows: –FIFOCFG defines the watermark of the DMAC channel FIFO. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. 4. 5. 6. 7. 8. 9. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller 17. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last descriptor, then program LLI_B(n).DMAC_DSCR with 0. 18.
8. 5. 6. 7. 8. 9. 35.9 Configure the fields of LLI_W(n).DMAC_CFGx for Channel x as follows: –FIFOCFG defines the watermark of the DMA channel FIFO. –DST_REP is set to zero. Address are contiguous. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. 9. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the AHB Layer ID.
35.9.2 SDIO Interrupts Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO interrupt on each slot can be enabled through the HSMCI Interrupt Enable Register. The SDIO interrupt is sampled regardless of the currently selected slot. 35.
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the error recovery procedure does not work as expected or there is another timeout, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets all device states. Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again.
35.12 HSMCI Transfer Done Timings 35.12.1 Definition The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished. 35.12.2 Read Access During a read access, the XFRDONE flag behaves as shown in Figure 35-11. Figure 35-11. XFRDONE During a Read Access CMD line HSMCI read CMD Card response The CMDRDY flag is released 8 tbit after the end of the card response. CMDRDY flag Data Last Block 1st Block Not busy flag XFRDONE flag 35.12.
35.13 Register Write Protection To prevent any single software error from corrupting HSMCI behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the “HSMCI Write Protection Mode Register” (HSMCI_WPMR). If a write access to a write-protected register is detected, the WPVS bit in the “HSMCI Write Protection Status Register” (HSMCI_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
35.14 High Speed MultiMedia Card Interface (HSMCI) User Interface Table 35-8.
35.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0xF0008000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN • MCIEN: Multi-Media Interface Enable 0: No effect. 1: Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0: No effect. 1: Disables the Multi-Media Interface.
35.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0xF0008004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 CLKODD 15 – 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” .
35.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0xF0008008 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” .
35.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0xF000800C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” . • SDCSEL: SDCard/SDIO Slot Value Name Description 0 SLOTA Slot A is selected.
35.14.
35.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0xF0008014 Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD).
• OPDCMD: Open Drain Command 0 (PUSHPULL): Push pull command. 1 (OPENDRAIN): Open drain command. • MAXLAT: Max Latency for Command to Response 0 (5): 5-cycle max latency. 1 (64): 64-cycle max latency. • TRCMD: Transfer Command Value Name Description 0 NO_DATA 1 START_DATA Start data transfer 2 STOP_DATA Stop data transfer 3 – No data transfer Reserved • TRDIR: Transfer Direction 0 (WRITE): Write. 1 (READ): Read.
35.14.7 HSMCI Block Register Name: HSMCI_BLKR Address: 0xF0008018 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the HSMCI Command Register (HSMCI_CMDR).
35.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0xF000801C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 CSTOMUL 4 3 2 1 0 CSTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” .
35.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0xF0008020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
35.14.
35.14.
35.14.12 HSMCI Status Register Name: HSMCI_SR Address: 0xF0008040 Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 – 14 – 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 – 6 – 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • CMDRDY: Command Ready 0: A command is in progress. 1: The last command has been sent.
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block. For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block. The NOTBUSY flag allows to deal with these different states. 0: The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 1: The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended.
• CSTOE: Completion Signal Time-out Error 0: No error. 1: The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR. Cleared by reading in the HSMCI_SR. • BLKOVRE: DMA Block Overrun Error 0: No error. 1: A new block of data is received and the DMA controller has not started to move the current pending block, a block overrun is raised. Cleared by reading in the HSMCI_SR.
35.14.13 HSMCI Interrupt Enable Register Name: HSMCI_IER Address: 0xF0008044 Access: Write-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 – 14 – 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 – 6 – 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
• BLKOVRE: DMA Block Overrun Error Interrupt Enable • DMADONE: DMA Transfer completed Interrupt Enable • FIFOEMPTY: FIFO empty Interrupt enable • XFRDONE: Transfer Done Interrupt enable • ACKRCV: Boot Acknowledge Interrupt Enable • ACKRCVE: Boot Acknowledge Error Interrupt Enable • OVRE: Overrun Interrupt Enable • UNRE: Underrun Interrupt Enable SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET] 11063K–ATARM–05-Nov-13 606
35.14.14 HSMCI Interrupt Disable Register Name: HSMCI_IDR Address: 0xF0008048 Access: Write-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 – 14 – 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 – 6 – 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
• BLKOVRE: DMA Block Overrun Error Interrupt Disable • DMADONE: DMA Transfer completed Interrupt Disable • FIFOEMPTY: FIFO empty Interrupt Disable • XFRDONE: Transfer Done Interrupt Disable • ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable • OVRE: Overrun Interrupt Disable • UNRE: Underrun Interrupt Disable SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET] 11063K–ATARM–05-Nov-13 608
35.14.
• BLKOVRE: DMA Block Overrun Error Interrupt Mask • DMADONE: DMA Transfer Completed Interrupt Mask • FIFOEMPTY: FIFO Empty Interrupt Mask • XFRDONE: Transfer Done Interrupt Mask • ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask • OVRE: Overrun Interrupt Mask • UNRE: Underrun Interrupt Mask SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET] 11063K–ATARM–05-Nov-13 610
35.14.16 HSMCI DMA Configuration Register Name: HSMCI_DMA Address: 0xF0008050 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 ROPT 11 – 10 – 9 – 8 DMAEN 7 – 6 5 CHKSIZE 4 3 – 2 – 1 0 OFFSET This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” .
35.14.17 HSMCI Configuration Register Name: HSMCI_CFG Address: 0xF0008054 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” .
35.14.18 HSMCI Write Protection Mode Register Name: HSMCI_WPMR Address: 0xF00080E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0: Disables the Write Protection if WPKEY corresponds to 0x4D4349 (“MCI” in ASCII). 1: Enables the Write Protection if WPKEY corresponds to 0x4D4349 (“MCI” in ASCII). See Section 35.
35.14.19 HSMCI Write Protection Status Register Name: HSMCI_WPSR Address: 0xF00080E8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of the HSMCI_WPSR. 1: A Write Protect Violation has occurred since the last read of the HSMCI_WPSR.
35.14.20 HSMCI FIFOx Memory Aperture Name: HSMCI_FIFOx[x=0..
36. Serial Peripheral Interface (SPI) 36.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
36.3 Block Diagram Figure 36-1. Block Diagram AHB Matrix DMA Ch.
36.4 Application Block Diagram Figure 36-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 MISO NC Slave 1 MOSI NPCS3 NSS SPCK MISO Slave 2 MOSI NSS 36.5 Signal Description Table 36-1.
36.6 Product Dependencies 36.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. Table 36-2.
36.7 Functional Description 36.7.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
Figure 36-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 36-4.
36.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
36.7.3.1 Master Mode Block Diagram Figure 36-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
36.7.3.2 Master Mode Flow Diagram Figure 36-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
Figure 36-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 36-7.
Figure 36-8. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 36.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. Fixed Peripheral Select: SPI exchanges data with only one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register).
36.7.3.7 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one NPCS line driven low at a time.
36.7.3.8 Peripheral Deselection without DMA During a transfer of more than one data on a Chip Select without the DMA, the SPI_TDR is loaded by the processor, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is detected high, the SPI_TDR can be reloaded.
Figure 36-10. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..3] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B A B DLYBCS DLYBCS PCS = B PCS = B Write SPI_TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE NPCS[0..
36.7.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0.
36.7.5 Write Protected Registers To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR). If a write access in a write protected register is detected, then the WPVS flag in the SPI Write Protection Status Register (SPI_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
36.8 Serial Peripheral Interface (SPI) User Interface Table 36-5.
36.8.1 SPI Control Register Name: SPI_CR Addresses: 0xF0000000 (0), 0xF0004000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI.
36.8.2 SPI Mode Register Name: SPI_MR Addresses: 0xF0000004 (0), 0xF0004004 (1) Access: Read-write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.
• PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
36.8.3 SPI Receive Data Register Name: SPI_RDR Addresses: 0xF0000008 (0), 0xF0004008 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
36.8.4 SPI Transmit Data Register Name: SPI_TDR Addresses: 0xF000000C (0), 0xF000400C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
36.8.
36.8.6 SPI Interrupt Enable Register Name: SPI_IER Addresses: 0xF0000014 (0), 0xF0004014 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = No effect. 1 = Enables the corresponding interrupt.
36.8.7 SPI Interrupt Disable Register Name: SPI_IDR Addresses: 0xF0000018 (0), 0xF0004018 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = No effect. 1 = Disables the corresponding interrupt.
36.8.8 SPI Interrupt Mask Register Name: SPI_IMR Addresses: 0xF000001C (0), 0xF000401C (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
36.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..3] Addresses: 0xF0000030 (0), 0xF0004030 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 3 2 1 0 CSAAT CSNAAT NCPHA CPOL This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. Note: SPI_CSRx registers must be written even if the user wants to use the defaults.
The BITS field determines the number of data bits transferred. Reserved values should not be used.
36.8.10 SPI Write Protection Mode Register Name: SPI_WPMR Addresses: 0xF00000E4 (0), 0xF00040E4 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x535049 (“SPI” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x535049 (“SPI” in ASCII).
36.8.11 SPI Write Protection Status Register Name: SPI_WPSR Addresses: 0xF00000E8 (0), 0xF00040E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
37. Timer Counter (TC) 37.1 Description The Timer Counter (TC) includes six identical 32-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
37.3 Block Diagram Figure 37-1.
37.4 Pin Name List Table 37-3. TC Pin List 37.5 Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O Product Dependencies 37.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 37-4.
37.6 Functional Description 37.6.1 TC Description The 6 channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 37-5 on page 662. 37.6.2 32-bit Counter Each channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
Figure 37-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK0 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 37-3.
37.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 37-4. The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
The following triggers are common to both modes: Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
Figure 37-5. Example of Transfer with DMAC ETRGEDG=1, LDRA=1, LDRB=2, ABETRG=0, TIOB TIOA RA RB Internal PDC trigger Transfer to System Memory RA RB RA RB T1 T2 T3 T4 T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK) ETRGEDG=3, LDRA=3, LDRB=0, ABETRG=0 TIOB TIOA RA Internal PDC trigger Transfer to System Memory RA RA RA RA T1 T2 T3 T4 T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK) 37.6.
MTIOA MTIOB 1 ABETRG CLKI If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel BURST MCK Synchronous Edge Detection R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT
37.6.11 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG MCK Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TIOB
37.6.12.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 37-8. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 37-9. RC Compare cannot be programmed to generate a trigger in this configuration.
37.6.12.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 37-10. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 37-11.
37.6.12.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 37-12. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 37-13.
37.6.12.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 37-14. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 37-15.
37.6.13 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
37.7 Timer Counter (TC) User Interface Table 37-5.
37.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Addresses: 0xF8008000 (0)[0], 0xF8008040 (0)[1], 0xF8008080 (0)[2], 0xF800C000 (1)[0], 0xF800C040 (1)[1], 0xF800C080 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0: No effect.
37.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
• ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock.
37.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..
• EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event. Value Name Description TIOB Direction 0 TIOB TIOB(1) Input 1 XC0 XC0 Output 2 XC1 XC1 Output 3 XC2 XC2 Output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
• ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BCPB: RB Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • B
• BSWTRG: Software Trigger Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET] 11063K–ATARM–05-Nov-13 669
37.7.4 TC Register AB Name: TC_RABx [x=0..2] Addresses: 0xF800800C (0)[0], 0xF800804C (0)[1], 0xF800808C (0)[2], 0xF800C00C (1)[0], 0xF800C04C (1)[1], 0xF800C08C (1)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RAB 23 22 21 20 RAB 15 14 13 12 RAB 7 6 5 4 RAB • RAB: Register A or Register B RAB contains the next unread capture Register A or Register B value in real time.
37.7.5 TC Counter Value Register Name: TC_CVx [x=0..2] Addresses: 0xF8008010 (0)[0], 0xF8008050 (0)[1], 0xF8008090 (0)[2], 0xF800C010 (1)[0], 0xF800C050 (1)[1], 0xF800C090 (1)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
37.7.6 TC Register A Name: TC_RAx [x=0..2] Addresses: 0xF8008014 (0)[0], 0xF8008054 (0)[1], 0xF8008094 (0)[2], 0xF800C014 (1)[0], 0xF800C054 (1)[1], 0xF800C094 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RA 23 22 21 20 RA 15 14 13 12 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time.
37.7.7 TC Register B Name: TC_RBx [x=0..2] Addresses: 0xF8008018 (0)[0], 0xF8008058 (0)[1], 0xF8008098 (0)[2], 0xF800C018 (1)[0], 0xF800C058 (1)[1], 0xF800C098 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RB 23 22 21 20 RB 15 14 13 12 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time.
37.7.8 TC Register C Name: TC_RCx [x=0..2] Addresses: 0xF800801C (0)[0], 0xF800805C (0)[1], 0xF800809C (0)[2], 0xF800C01C (1)[0], 0xF800C05C (1)[1], 0xF800C09C (1)[2] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
37.7.9 TC Status Register Name: TC_SRx [x=0..
• CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0: TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1: TIOB is high.
37.7.10 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Addresses: 0xF8008024 (0)[0], 0xF8008064 (0)[1], 0xF80080A4 (0)[2], 0xF800C024 (1)[0], 0xF800C064 (1)[1], 0xF800C0A4 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect.
37.7.11 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Addresses: 0xF8008028 (0)[0], 0xF8008068 (0)[1], 0xF80080A8 (0)[2], 0xF800C028 (1)[0], 0xF800C068 (1)[1], 0xF800C0A8 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect.
37.7.12 TC Interrupt Mask Register Name: TC_IMRx [x=0..
37.7.13 TC Block Control Register Name: TC_BCR Addresses: 0xF80080C0 (0), 0xF800C0C0 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
37.7.
38. Pulse Width Modulation Controller (PWM) 38.1 Description The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
38.3 Block Diagram Figure 38-1. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Period Channel PWMx Update Duty Cycle Clock Selector Comparator PWMx Counter PIO PWM0 Channel Period PWM0 Update Duty Cycle Clock Selector PMC MCK Clock Generator Comparator PWM0 Counter APB Interface Interrupt Generator Interrupt Controller APB 38.4 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 38-1.
38.5 Product Dependencies 38.5.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.
38.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. Clocked by the system clock, MCK, the clock generator module provides 13 clocks. Each channel can independently choose one of the clock generator outputs. Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 38.6.1 PWM Clock Generator Figure 38-2.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. 38.6.2 PWM Channel 38.6.2.1 Block Diagram Figure 38-3.
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2*X*CPRD*DIVA ) ( 2*X*CPRD*DIVB ) ---------------------------------------------------- or ---------------------------------------------------MCK MCK the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
Figure 38-5.
38.6.3 PWM Controller Operations 38.6.3.1 Initialization Before enabling the output channel, this channel must have been configured by the software application: Configuration of the clock generator if DIVA and DIVB are required Selection of the clock for each channel (CPRE field in the PWM_CMRx register) Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
Figure 38-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.
38.7 Pulse Width Modulation Controller (PWM) User Interface Table 38-4.
38.7.1 PWM Mode Register Name: PWM_MR Address: 0xF8034000 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 10 DIVB 15 – 14 – 13 – 12 – 11 7 6 5 4 3 PREA 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor Value Name Description 0 CLK_OFF CLKA, CLKB clock is turned off 1 CLK_DIV1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 – CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
38.7.2 PWM Enable Register Name: PWM_ENA Address: 0xF8034004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.
38.7.3 PWM Disable Register Name: PWM_DIS Address: 0xF8034008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x.
38.7.4 PWM Status Register Name: PWM_SR Address: 0xF803400C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
38.7.5 PWM Interrupt Enable Register Name: PWM_IER Address: 0xF8034010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x.
38.7.6 PWM Interrupt Disable Register Name: PWM_IDR Address: 0xF8034014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
38.7.7 PWM Interrupt Mask Register Name: PWM_IMR Address: 0xF8034018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled.
38.7.8 PWM Interrupt Status Register Name: PWM_ISR Address: 0xF803401C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
38.7.9 PWM Channel Mode Register Name: PWM_CMR[0..
38.7.10 PWM Channel Duty Cycle Register Name: PWM_CDTY[0..3] Address: 0xF8034204 [0], 0xF8034224 [1], 0xF8034244 [2], 0xF8034264 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 32 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
38.7.11 PWM Channel Period Register Name: PWM_CPRD[0..3] Address: 0xF8034208 [0], 0xF8034228 [1], 0xF8034248 [2], 0xF8034268 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 32 bits (internal channel counter size) are significant.
38.7.12 PWM Channel Counter Register Name: PWM_CCNT[0..3] Address: 0xF803420C [0], 0xF803422C [1], 0xF803424C [2], 0xF803426C [3] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: the channel is enabled (writing CHIDx in the PWM_ENA register).
38.7.13 PWM Channel Update Register Name: PWM_CUPD[0..3] Address: 0xF8034210 [0], 0xF8034230 [1], 0xF8034250 [2], 0xF8034270 [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD CUPD: Channel Update Register This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
39. Two-wire Interface (TWI) 39.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
39.2 Embedded Characteristics Two TWIs Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices(1) One, Two or Three Bytes for Slave Address Sequential Read-write Operations Master, Multi-master and Slave Mode Operation Bit Rate: Up to 400 Kbit/s General Call Supported in Slave mode SMBUS Quick Command Supported in Master Mode Connection to DMA Controller (DMA) Channel Capabilities Optimizes Data Transfers Note: 39.3 1.
39.4 Block Diagram Figure 39-1. Block Diagram APB Bridge TWCK PIO PMC MCK TWD Two-wire Interface TWI Interrupt 39.5 Interrupt Controller Application Block Diagram Figure 39-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull-up value as given by the I²C Standard 39.5.1 I/O Lines Description Table 39-3.
39.6 Product Dependencies 39.6.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 39-2). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines.
39.7 Functional Description 39.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 39-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 39-3). A high-to-low transition on the TWD line while TWCK is high defines the START condition.
39.8 Master Mode 39.8.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 39.8.2 Application Block Diagram Figure 39-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull-up value as given by the I²C Standard 39.8.
Figure 39-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 39-7.
Figure 39-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 39.8.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device.
Figure 39-9. Master Read with One Data Byte S TWD DADR R A DATA NA P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 39-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) NA P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read Figure 39-11.
39.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 39.8.6.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
Figure 39-13. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A A IADR(15:8) IADR(7:0) A Sr DADR R A DATA NA P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A Sr W A IADR(7:0) A Sr R A DADR R A DATA NA P One byte internal address TWD S DADR DADR DATA NA P 39.8.6.
39.8.7.2 Data Receive with the DMA The DMA transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed without DMA to ensure that the exact number of bytes are received whatever the system bus latency conditions encountered during the end of buffer transfer period. In slave mode, the number of characters to receive must be known in order to configure the DMA. 1. Initialize the DMA (channels, memory pointers, size -2, etc.); 2.
39.8.9 Read-write Flowcharts The following flowcharts shown in Figure 39-17 on page 718, Figure 39-18 on page 719, Figure 39-19 on page 720, Figure 39-20 on page 721 and Figure 39-21 on page 722 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 39-16.
Figure 39-17.
Figure 39-18.
Figure 39-19.
Figure 39-20.
Figure 39-21.
39.9 Multi-master Mode 39.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
Figure 39-22. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 39-23.
Figure 39-24.
39.10 Slave Mode 39.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 39.10.2 Application Block Diagram Figure 39-25.
39.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 39-27 on page 728. 39.10.4.
39.10.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
39.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 39-30 describes the clock synchronization in Read mode. Figure 39-30.
Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command. Figure 39-32 describes the repeated start + reversal from Write to Read mode. Figure 39-32. Repeated Start + Reversal from Write to Read Mode DATA2 TWI_THR TWD S SADR W A DATA0 TWI_RHR A DATA1 A DATA0 Sr SADR R A DATA3 DATA2 A DATA3 NA P DATA1 SVACC SVREAD TXRDY RXRDY Read TWI_RHR EOSACC TXCOMP Cleared after read As soon as a START is detected Notes: 1.
39.10.7 Read Write Flowcharts The flowchart shown in Figure 39-33 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 39-33.
39.11 Write Protection System In order to bring security to the TWI, a write protection system has been implemented. The write protection mode prevents the write of the “TWI Clock Waveform Generator Register” and the “TWI Slave Mode Register”. When this mode is enabled and one of the protected registers is written, an error is generated in the “TWI Write Protection Status Register” and the register write request is canceled.
39.12 Two-wire Interface (TWI) User Interface Table 39-7.
39.12.1 TWI Control Register Name: TWI_CR Addresses: 0xF8010000 (0), 0xF8014000 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register.
• SVDIS: TWI Slave Mode Disabled 0: No effect. 1: The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0: No effect. 1: If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset.
39.12.
39.12.3 TWI Slave Mode Register Name: TWI_SMR Addresses: 0xF8010008 (0), 0xF8014008 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the “TWI Write Protection Mode Register”.
39.12.4 TWI Internal Address Register Name: TWI_IADR Addresses: 0xF801000C (0), 0xF801400C (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
39.12.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Addresses: 0xF8010010 (0), 0xF8014010 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV This register can only be written if the WPEN bit is cleared in the “TWI Write Protection Mode Register”. TWI_CWGR is only used in Master mode.
39.12.6 TWI Status Register Name: TWI_SR Addresses: 0xF8010020 (0), 0xF8014020 (1) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0: During the length of the current frame.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 39-26 on page 727, Figure 39-29 on page 729, Figure 39-31 on page 730 and Figure 39-32 on page 731. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
• SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0: The clock is not stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 39-29 on page 729 and Figure 39-30 on page 730. • EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0: A slave access is being performing. 1: The Slave Access is finished.
39.12.7 TWI Interrupt Enable Register Name: TWI_IER Addresses: 0xF8010024 (0), 0xF8014024 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
39.12.8 TWI Interrupt Disable Register Name: TWI_IDR Addresses: 0xF8010028 (0), 0xF8014028 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
39.12.9 TWI Interrupt Mask Register Name: TWI_IMR Addresses: 0xF801002C (0), 0xF801402C (1) Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled.
39.12.
39.12.
39.12.12 TWI Write Protection Mode Register Name: TWI_WPMR Addresses: 0xF80100E4 (0), 0xF80140E4 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x545749 (“TWI” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x545749 (“TWI” in ASCII).
39.12.13 TWI Write Protection Status Register Name: TWI_WPSR Addresses: 0xF80100E8 (0), 0xF80140E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 23 22 21 20 WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the TWI_WPSR. 1: A Write Protect Violation has occurred since the last read of the TWI_WPSR.
40. Universal Synchronous Asynchronous Receiver Transceiver (USART) 40.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
Parity sending and verification can be disabled Automatic Checksum calculation/sending and verification Checksum sending and verification can be disabled Support both “Classic” and “Enhanced” checksum types Full LIN error checking and reporting Frame Slot Mode: Master allocates slots to the scheduled frames automatically Generation of the Wakeup signal Test Modes Supports Connection of: Remote Loopback, Local Loopback, Automatic Echo Two DMA Controller Channels (DM
40.3 Block Diagram Figure 40-1.
40.4 Application Block Diagram Figure 40-2.
40.5 I/O Lines Description Table 40-1. I/O Line Description Name Description Type Active Level SCK Serial Clock I/O — I/O — Input — Input Low Output Low Transmit Serial Data TXD or Master Out Slave In (MOSI) in SPI Master Mode or Master In Slave Out (MISO) in SPI Slave Mode Receive Serial Data RXD or Master In Slave Out (MISO) in SPI Master Mode or Master Out Slave In (MOSI) in SPI Slave Mode Clear to Send CTS or Slave Select (NSS) in SPI Slave Mode Request to Send RTS 40.
Table 40-2. I/O Lines USART3 CTS3 PC25 B USART3 RTS3 PC24 B USART3 RXD3 PC23 B USART3 SCK3 PC26 B USART3 TXD3 PC22 B 40.6.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later.
40.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: 5- to 9-bit full-duplex asynchronous serial communication MSB- or LSB-first 1, 1.
40.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
Baud Rate Calculation Example Table 40-4 shows calculations of CD to obtain a baud rate at 38,400 bit/s for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 40-4. Baud Rate Example (OVER = 0) Source Clock (MHz) Expected Baud Rate (Bit/s) Calculation Result CD Actual Baud Rate (Bit/s) Error 3,686,400 38,400 6.00 6 38,400.00 0.00% 4,915,200 38,400 8.00 8 38,400.00 0.00% 5,000,000 38,400 8.14 8 39,062.50 1.
The modified architecture is presented below: Figure 40-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 16-bit Counter 2 Glitch-free Logic 3 FIDI >1 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 40.7.1.3 Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in the US_BRGR.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 40-6. Table 40-6. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 40-7 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 40-7.
40.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the US_CR. However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently.
Figure 40-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 40.7.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1.
Figure 40-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR register.
Figure 40-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd Command Sync start frame delimiter SFD Manchester encoded data DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e., respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur.
If RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 40-14. The sample pulse rejection mechanism applies. In order to increase the compatibility the RXIDLV bit in the US_MAN register allows to inform the USART block of the Rx line idle state value (Rx line undriven), it can be either level one (pull-up) or level zero (pull-down). By default this bit is set to one (Rx line is at level 1 if undriven). Figure 40-14.
When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register.
Figure 40-18. ASK Modulator Output 1 0 0 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 Figure 40-19. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 40.7.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate clock.
40.7.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the US_CSR rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the US_CR with the RSTSTA (Reset Status) bit to 1. Figure 40-21.
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the US_CSR. The PARE bit can be cleared by writing the US_CR with the RSTSTA bit to 1. Figure 40-22 illustrates the parity bit status setting and clearing. Figure 40-22. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE Parity Error Detect Time Flags Report Time RXRDY 40.7.3.
Figure 40-23. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 40-9 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. Table 40-9. Maximum Timeguard Length Depending on Baud Rate Baud Rate (Bit/s) Bit Time (µs) Timeguard (ms) 1,200 833 212.50 9,600 104 26.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO.
40.7.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1.
Figure 40-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 40.7.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR.
Figure 40-28. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 40.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported.
When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 40-30. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D2 D1 D4 D3 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 40-31.
40.7.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the US_CSR. 40.7.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 40-32.
Figure 40-33 shows an example of character transmission. Figure 40-33. IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 0 1 1 0 0 1 1 0 1 TXD 3 16 Bit Period Bit Period 40.7.5.2 IrDA Baud Rate Table 40-12 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 40-12.
40.7.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
Figure 40-36. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 40.7.7 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.
Operation in SPI Master Mode is programmed by writing 0xE to the USART_MODE field in the Mode Register (US_MR). In this case the SPI lines must be connected as described below: The MOSI line is driven by the output pin TXD The MISO line drives the input pin RXD The SCK line is driven by the output pin SCK The NSS line is driven by the output pin RTS Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the Mode Register.
pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 40-14. SPI Bus Protocol Mode SPI Bus Protocol Mode CPOL CPHA 0 0 1 1 0 0 2 1 1 3 1 0 Figure 40-37.
Figure 40-38.
40.7.7.4 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 762. 40.7.7.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (US_THR). An additional condition for transmitting a character can be added when the USART is configured in SPI master mode. In the USART_MR, the value configured on INACK field can prevent any character transmission (even if US_THR has been written) while the receiver side is not ready (character not read).
40.7.8 LIN Mode The LIN Mode provides Master node and Slave node connectivity on a LIN bus. The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The main properties of the LIN bus are: Single Master/Multiple Slaves concept Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine.
As soon as the Synch Break Field is transmitted, the flag LINBK in the Channel Status Register (US_CSR) is set to 1. Likewise, as soon as the Identifier Field is sent, the flag bit LINID in the US_CSR is set to 1. These flags are reset by writing a one to the bit RSTSTA in the Control register (US_CR). Figure 40-39.
Figure 40-40. Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINBK LINID US_LINIR Write RSTSTA=1 in US_CR 40.7.8.8 Slave Node Synchronization The synchronization is done only in Slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field.
Figure 40-42.
40.7.8.9 Identifier Parity A protected identifier consists of two subfields; the identifier and the identifier parity. Bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. The USART interface can generate/check these parity bits, but this feature can also be disabled.
40.7.8.11 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1). The user can choose between these two modes by the DLM bit of the LIN Mode register (US_LINMR): DLM = 0: The response data length is configured by the user via the DLC field of the US_LINMR.
If the Frame Slot Mode is disabled (FSDIS = 1) and a frame transfer has been completed, the TXRDY flag is set again immediately. The TFrame_Maximum is calculated as below: If the Checksum is sent (CHKDIS = 0): THeader_Nominal = 34 x Tbit TResponse_Nominal = 10 x (NData + 1) x Tbit TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1)(1) TFrame_Maximum = 1.
This error is reported by flag LINIPE in the US_CSR. Checksum Error This error is generated in Master of Slave node configuration, if the received checksum is wrong. This flag can be set to “1” only if the checksum feature is enabled (CHKDIS = 0). This error is reported by flag LINCE in the US_CSR.
Figure 40-45. Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Checksum Data N TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 40-46.
Figure 40-47. Master Node Configuration, NACT = IGNORE Frame slot = TFrame_Maximum Frame Break Interframe space Response space Header Data3 Synch Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR LINTC Slave Node Configuration Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. Write USART_MODE in US_MR to select the LIN mode and the Slave Node configuration.
Figure 40-48. Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 40-49. Slave Node Configuration, NACT = SUBSCRIBE Break Synch Protected Identifier Data 1 Data N-1 TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 40-50.
40.7.8.16 LIN Frame Handling With the DMAC The USART can be used in association with the DMAC in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. The DMAC uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The DMAC always writes in the Transmit Holding register (US_THR) and it always reads in the Receive Holding register (US_RHR). The size of the data written or read by the DMAC in the USART is always a byte.
Figure 40-52. Master Node with DMAC (PDCM = 0) WRITE BUFFER WRITE BUFFER IDENTIFIER IDENTIFIER NODE ACTION = PUBLISH APB bus READ BUFFER (Peripheral) DMA Controller | | | | NODE ACTION = SUBSCRIBE APB bus DATA 0 USART3 LIN CONTROLLER TXRDY DATA 0 (Peripheral) DMA Controller RXRDY USART3 LIN CONTROLLER TXRDY | | | | DATA N DATA N Slave Node Configuration In this configuration, the DMAC transfers only the DATA.
40.7.8.18 Bus Idle Time-out If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. In the LIN 2.0 specification, this time-out is fixed at 4 seconds. In the LIN 1.3 specification, it is fixed at 25,000 Tbits. In Slave Node configuration, the Receiver Time-out detects an idle condition on the RXD line.
40.7.9.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 40-55. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 40-55. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 40.7.9.
40.7.10 Write Protection Registers To prevent any single software error that may corrupt USART behavior, certain address spaces can be write protected by setting the WPEN bit in the USART Write Protect Mode Register (US_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
40.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 40-17.
40.8.1 USART Control Register Name: US_CR Addresses: 0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS 18 RTSEN 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see “USART Control Register (SPI_MODE)” . • RSTRX: Reset Receiver 0: No effect.
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
40.8.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Addresses: 0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” . • RSTRX: Reset Receiver 0: No effect.
• RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits OVRE, UNRE in US_CSR. • FCS: Force SPI Chip Select Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): 0: No effect. 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). • RCS: Release SPI Chip Select Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): 0: No effect.
40.8.3 USART Mode Register Name: US_MR Addresses: 0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3) Access: Read-write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 15 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” .
• CHRL: Character Length Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode.
• CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
40.8.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Addresses: 0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 – 18 – 17 – 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 7 6 5 4 3 2 1 0 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” .
• CHMODE: Channel Mode Value Name Description 0 NORMAL Normal Mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • CPOL: SPI Clock Polarity Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF): 0: The inactive state value of SPCK is logic level zero.
40.8.5 USART Interrupt Enable Register Name: US_IER Addresses: 0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” .
40.8.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Addresses: 0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” .
40.8.7 USART Interrupt Enable Register (LIN_MODE) Name: US_IER (LIN_MODE) Addresses: 0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access: Write-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 LINTC 14 LINID 13 LINBK 12 – 11 – 10 – 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xA or 0xB in “USART Mode Register” .
40.8.8 USART Interrupt Disable Register Name: US_IDR Addresses: 0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” .
40.8.9 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Addresses: 0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” .
40.8.
40.8.11 USART Interrupt Mask Register Name: US_IMR Addresses: 0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)” .
40.8.12 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Addresses: 0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” .
40.8.13 USART Interrupt Mask Register (LIN_MODE) Name: US_IMR (LIN_MODE) Addresses: 0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access: Read-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 LINTC 14 LINID 13 LINBK 12 – 11 – 10 – 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xA or 0xB in “USART Mode Register” .
40.8.14 USART Channel Status Register Name: US_CSR Addresses: 0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” .
• TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register.
40.8.15 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Addresses: 0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” .
40.8.
• TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • LINBK: LIN Break Sent or LIN Break Received Applicable if USART operates in LIN Master Mode (USART_MODE = 0xA): 0: No LIN Break has been sent since the last RSTSTA.
• LINCE: LIN Checksum Error 0: No LIN Checksum Error has been detected since the last RSTSTA. 1: A LIN Checksum Error has been detected since the last RSTSTA. • LINSNRE: LIN Slave Not Responding Error 0: No LIN Slave Not Responding Error has been detected since the last RSTSTA. 1: A LIN Slave Not Responding Error has been detected since the last RSTSTA.
40.8.17 USART Receive Holding Register Name: US_RHR Addresses: 0xF801C018 (0), 0xF8020018 (1), 0xF8024018 (2), 0xF8028018 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
40.8.18 USART Transmit Holding Register Name: US_THR Addresses: 0xF801C01C (0), 0xF802001C (1), 0xF802401C (2), 0xF802801C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
40.8.19 USART Baud Rate Generator Register Name: US_BRGR Addresses: 0xF801C020 (0), 0xF8020020 (1), 0xF8024020 (2), 0xF8028020 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” .
40.8.20 USART Receiver Time-out Register Name: US_RTOR Addresses: 0xF801C024 (0), 0xF8020024 (1), 0xF8024024 (2), 0xF8028024 (3) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” . • TO: Time-out Value 0: The Receiver Time-out is disabled.
40.8.21 USART Transmitter Timeguard Register Name: US_TTGR Addresses: 0xF801C028 (0), 0xF8020028 (1), 0xF8024028 (2), 0xF8028028 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” . • TG: Timeguard Value 0: The Transmitter Timeguard is disabled.
40.8.22 USART FI DI RATIO Register Name: US_FIDI Addresses: 0xF801C040 (0), 0xF8020040 (1), 0xF8024040 (2), 0xF8028040 (3) Access: Read-write Reset: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 FI_DI_RATIO 7 6 5 4 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” .
40.8.23 USART Number of Errors Register Name: US_NER Addresses: 0xF801C044 (0), 0xF8020044 (1), 0xF8024044 (2), 0xF8028044 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE = 0x4 or 0x6 in “USART Mode Register” . • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer.
40.8.24 USART IrDA FILTER Register Name: US_IF Addresses: 0xF801C04C (0), 0xF802004C (1), 0xF802404C (2), 0xF802804C (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE = 0x8 in “USART Mode Register” . This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” .
40.8.25 USART Manchester Configuration Register Name: US_MAN Addresses: 0xF801C050 (0), 0xF8020050 (1), 0xF8024050 (2), 0xF8028050 (3) Access: Read-write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 17 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” .
• RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register. • DRIFT: Drift Compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.
40.8.26 USART LIN Mode Register Name: US_LINMR Addresses: 0xF801C054 (0), 0xF8020054 (1), 0xF8024054 (2), 0xF8028054 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 0 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP NACT This register is relevant only if USART_MODE = 0xA or 0xB in “USART Mode Register” .
• FSDIS: Frame Slot Mode Disable 0: The Frame Slot Mode is enabled. 1: The Frame Slot Mode is disabled. • WKUPTYP: Wakeup Signal Type 0: Setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: Setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. • DLC: Data Length Control 0–255: Defines the response data length if DLM = 0,in that case the response data length is equal to DLC+1 bytes.
40.8.27 USART LIN Identifier Register Name: US_LINIR Addresses: 0xF801C058 (0), 0xF8020058 (1), 0xF8024058 (2), 0xF8028058 (3) Access: Read-write or Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR This register is relevant only if USART_MODE = 0xA or 0xB in “USART Mode Register” .
40.8.28 USART LIN Baud Rate Register Name: US_LINBRR Addresses: 0xF801C05C (0), 0xF802005C (1), 0xF802405C (2), 0xF802805C (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 LINFP 16 15 14 13 12 11 10 9 8 3 2 1 0 LINCD 7 6 5 4 LINCD This register is relevant only if USART_MODE = 0xA or 0xB in “USART Mode Register” . Returns the baud rate value after the synchronization process completion.
40.8.29 USART Write Protect Mode Register Name: US_WPMR Addresses: 0xF801C0E4 (0), 0xF80200E4 (1), 0xF80240E4 (2), 0xF80280E4 (3) Access: Read-write Reset: See Table 40-17 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
40.8.30 USART Write Protect Status Register Name: US_WPSR Addresses: 0xF801C0E8 (0), 0xF80200E8 (1), 0xF80240E8 (2), 0xF80280E8 (3) Access: Read-only Reset: See Table 40-17 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the US_WPSR.
41. Universal Asynchronous Receiver Transmitter (UART) 41.1 Description The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with DMA controller permits packet handling for these tasks with processor time reduced to a minimum. 41.
41.3 Block Diagram Figure 41-1. UART Functional Block Diagram Peripheral Bridge DMA Controller APB UAR T UTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive URXD Interrupt Control uart_irq Table 41-1.
41.4 Product Dependencies 41.4.1 I/O Lines The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO Controller to enable I/O line operations of the UART. Table 41-2. I/O Lines Instance Signal I/O Line Peripheral UART0 URXD0 PC9 C UART0 UTXD0 PC8 C UART1 URXD1 PC17 C UART1 UTXD1 PC16 C 41.4.2 Power Management The UART clock is controllable through the Power Management Controller.
41.5.2 Receiver 41.5.2.1 Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped.
41.5.2.3 Receiver Ready When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read. Figure 41-5. Receiver Ready S URXD D0 D1 D2 D3 D4 D5 D6 D7 D0 S P D1 D2 D3 D4 D5 D6 D7 P RXRDY Read UART_RHR 41.5.2.
41.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit RSTSTA at 1. Figure 41-8.
41.5.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register UART_SR. The transmission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written character is transferred from UART_THR to the Shift Register. The TXRDY bit remains high until a second character is written in UART_THR.
Figure 41-11.
41.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 41-3.
41.6.1 UART Control Register Name: UART_CR Addresses: 0xF8040000 (0), 0xF8044000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
41.6.
41.6.
41.6.
41.6.
41.6.6 UART Status Register Name: UART_SR Addresses: 0xF8040014 (0), 0xF8044014 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
41.6.7 UART Receiver Holding Register Name: UART_RHR Addresses: 0xF8040018 (0), 0xF8044018 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
41.6.8 UART Transmit Holding Register Name: UART_THR Addresses: 0xF804001C (0), 0xF804401C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
41.6.
42. Analog-to-Digital Converter (ADC) 42.1 Description The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to Figure 42-1, "Analog-to-Digital Converter Block Diagram with Touchscreen mode". It also integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions of 12 analog lines. The conversions extend from 0V to the voltage carried on pin ADVREF. The ADC supports the 8-bit or 10-bit resolution mode.
42.
42.3 Block Diagram Figure 42-1.
42.5 Product Dependencies 42.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled. 42.5.
42.6 Functional Description 42.6.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data requires Tracking Clock cycles as defined in the field TRACKTIM of the “ADC Mode Register” on page 886. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The tracking phase starts during the conversion of the previous channel.
42.6.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the TAG option in the ADC_EMR, the ADC_LCDR presents the channel number associated to the last converted data in the CHNB field. The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set.
Figure 42-4.
42.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1. The hardware trigger can be selected by the TRGMOD field in the “ADC Trigger Register” between: any edge, either rising or falling or both, detected on the external trigger pin, TSADTRG. the Pen Detect, depending on how the PENDET bit is set in the “ADC Touchscreen Mode Register”.
42.6.7 Comparison Window The ADC Controller features automatic comparison functions. It compares converted values to a low threshold or a high threshold or both, according to the CMPMODE function chosen in the Extended Mode Register (ADC_EMR). The comparison can be done on all channels or only on the channel specified in CMPSEL field of ADC_EMR. To compare all channels the CMP_ALL parameter of ADC_EMR should be set.
42.7 Touchscreen 42.7.1 Touchscreen Mode The TSMODE parameter of “ADC Touchscreen Mode Register” is used to enable/disable the Touchscreen functionality, to select the type of screen (4-wire or 5-wire) and, in the case of a 4-wire screen, to activate (or not) the pressure measurement. In 4-wire mode, channel 0, 1, 2 and 3 must not be used for classic ADC conversions. Likewise, in 5-wire mode, channel 0, 1, 2, 3, and 4 must not be used for classic ADC conversions. 42.7.
42.7.3 4-wire Position Measurement Method As shown in Figure 42-6, to detect the position of a contact, a supply is first applied from top to bottom. Due to the linear resistance of the film, there is a voltage gradient from top to bottom. When a contact is performed on the screen, the voltage propagates at the point the two surfaces come into contact with the second film.
42.7.4 4-wire Pressure Measurement Method The method to measure the pressure (Rp) applied to the touchscreen is based on the known resistance of the X-Panel resistance (Rxp). Three conversions (Xpos,Z1,Z2) are necessary to determine the value of Rp (Zaxis resistance). Rp = Rxp*(Xpos/1024)*[(Z2/Z1)-1] Figure 42-8.
Figure 42-9. 5-Wire principle UL Pen Contact Resistive layer UR Sense LL LR Conductive Layer UL UR VDDANA VDDANA for Yp GND for Xp Sense LL LR VDDANA for Xp GND for Yp GND 42.7.6 5-wire Position Measurement Method In an application only monitoring clicks, 100 points per second is typically needed. For handwriting or motion detection, the number of measurements to consider is approximately 200 points per second.
Figure 42-10.
42.7.7 Sequence and Noise Filtering The ADC Controller can manage ADC conversions and Touchscreen measurement. On each trigger event the sequence of ADC conversions is performed as described in Section 42.6.6 ”Sleep Mode and Conversion Sequencer”. The Touchscreen measure frequency can be specified in number of trigger events by writing the TSFREQ parameter in the “ADC Touchscreen Mode Register”.
42.7.9 Pen Detect Method When there is no contact, it is not necessary to perform a conversion. However, it is important to detect a contact by keeping the power consumption as low as possible. The implementation polarizes one panel by closing the switch on (XP/UL) and ties the horizontal panel by an embedded resistor connected to YM / Sense. This resistor is enabled by a fifth switch. Since there is no contact, no current is flowing and there is no related power consumption.
42.7.10 Buffer Structure The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR) the structure differs.
42.7.10.2 Touchscreen Channels Only When only touchscreen conversions are required (i.e. TSMODE differs from 0 in ADC_TSMR register and ADC_CHSR equals 0), the structure of data within the buffer is defined by the ADC_TSMR register. When TSMODE = 1 or 3, each trigger event adds 2 half-words in the buffer (assuming TSAV = 0), first half-word being XPOS of ADC_XPOSR register then YPOS of ADC_YPOSR register. If TSAV/TSFREQ differs from 0, the data structure remains unchanged.
Figure 42-14. Buffer Structure when only Touchscreen Channels are Enabled Assuming ADC_TSMR(TSMOD) = 1 or 3 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1 trig.event1 DMA Buffer Structure trig.event2 0 ADC_XPOSR 1 ADC_YPOSR Assuming ADC_TSMR(TSMOD) =1 or 3 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0 DMA Transfer trig.event1 Base Address (BA) DMA Buffer Structure BA + 0x02 trig.
42.7.10.3 Interleaved Channels When both classic ADC channels (CH4/CH5 up to CH12 are set in ADC_CHSR) and touchscreen conversions are required (TSMODE differs from 0 in ADC_TSMR register) the structure of the buffer differs according to TSAV and TSFREQ values. If TSFREQ differs from 0, not all events generate touchscreen conversions, therefore buffer structure is based on 2TSFREQ trigger events. Given a TSFREQ value, the location of touchscreen conversion results depends on TSAV value.
Figure 42-15. Buffer Structure when Classic ADC and Touchscreen Channels are Interleaved Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) =1 trig.event1 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 8 DMA Buffer Structure trig.event2 Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) = 0 trig.event1 DMA Buffer Structure trig.
42.7.10.4 Pen Detection Status If the pen detection measure is enabled (PENDET is set in ADC_TSMR register), the XPOS, YPOS, Z1, Z2 values transmitted to the buffer through ADC_LCDR register are cleared (including the CHNB field), if the PENS flag of ADC_ISR register is 0. When the PENS flag is set, XPOS, YPOS, Z1, Z2 are normally transmitted.
42.7.11 Write Protected Registers To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register (ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
42.8 Analog-to-Digital Converter (ADC) User Interface Table 42-4.
42.8.1 ADC Control Register Name: ADC_CR Address: 0xF804C000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TSCALIB 1 START 0 SWRST • SWRST: Software Reset 0: No effect. 1: Resets the ADC simulating a hardware reset. • START: Start Conversion 0: No effect. 1: Begins analog-to-digital conversion. • TSCALIB: Touchscreen Calibration 0: No effect.
42.8.2 ADC Mode Register Name: ADC_MR Address: 0xF804C004 Access: Read-write 31 USEQ 30 – 29 – 28 – 27 23 – 22 DIV1 21 – 20 – 19 15 14 13 12 26 25 24 17 16 TRACKTIM 18 STARTUP 11 10 9 8 3 2 – 1 0 – PRESCAL 7 – 6 5 SLEEP – 4 LOWRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 910. • LOWRES: Resolution Value Name Description 0 BITS_10 10-bit resolution.
Value Name Description 10 SUT640 640 periods of ADCClock 11 SUT704 704 periods of ADCClock 12 SUT768 768 periods of ADCClock 13 SUT832 832 periods of ADCClock 14 SUT896 896 periods of ADCClock 15 SUT960 960 periods of ADCClock • TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) * ADCClock periods. • USEQ: Use Sequence Enable Value Name Description 0 NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.
42.8.3 ADC Channel Sequence 1 Register Name: ADC_SEQR1 Address: 0xF804C008 Access: Read-write 31 30 29 28 27 26 USCH8 23 22 21 20 19 18 USCH6 15 14 13 6 24 17 16 9 8 1 0 USCH5 12 11 10 USCH4 7 25 USCH7 USCH3 5 4 USCH2 3 2 USCH1 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
42.8.4 ADC Channel Sequence 2 Register Name: ADC_SEQR2 Address: 0xF804C00C Access: Read-write 31 30 29 28 27 26 – 23 22 21 20 19 18 – 15 14 13 6 24 17 16 9 8 1 0 – 12 11 10 – 7 25 – USCH11 5 4 USCH10 3 2 USCH9 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • USCHx: User Sequence Number x The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this field.
42.8.5 ADC Channel Enable Register Name: ADC_CHER Address: 0xF804C010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel.
42.8.6 ADC Channel Disable Register Name: ADC_CHDR Address: 0xF804C014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel.
42.8.7 ADC Channel Status Register Name: ADC_CHSR Address: 0xF804C018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled.
42.8.8 ADC Last Converted Data Register Name: ADC_LCDR Address: 0xF804C020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
42.8.
42.8.
42.8.
42.8.12 ADC Interrupt Status Register Name: ADC_ISR Address: 0xF804C030 Access: Read-only 31 PENS 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0: The corresponding analog channel is disabled, or the conversion is not finished.
• NOPEN: No Pen contact 0: No loss of pen contact since the last read of ADC_ISR. 1: At least one loss of pen contact since the last read of ADC_ISR. • PENS: Pen detect Status 0: The pen does not press the screen. 1: The pen presses the screen. Note: PENS is not a source of interruption.
42.8.13 ADC Overrun Status Register Name: ADC_OVER Address: 0xF804C03C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 • OVREx: Overrun Error x 0: No overrun error on the corresponding channel since the last read of ADC_OVER.
42.8.14 ADC Extended Mode Register Name: ADC_EMR Address: 0xF804C040 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 CMPALL 8 – 7 6 5 4 3 – 2 – 1 0 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
42.8.15 ADC Compare Window Register Name: ADC_CWR Address: 0xF804C044 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • LOWTHRES: Low Threshold Low threshold associated to compare settings of the ADC_EMR register.
42.8.16 ADC Channel Data Register Name: ADC_CDRx [x=0..11] Address: 0xF804C050 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
42.8.17 ADC Analog Control Register Name: ADC_ACR Address: 0xF804C094 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0 PENDETSENS This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • PENDETSENS: Pen Detection Sensitivity Allows to modify the pen detection input pull-up resistor value.
42.8.18 ADC Touchscreen Mode Register Name: ADC_TSMR Address: 0xF804C0B0 Access: Read-write 31 30 29 28 27 – 26 – 18 PENDBC 23 – 22 NOTSDMA 21 – 20 – 19 15 – 14 – 13 – 12 – 11 7 – 6 – 5 4 3 – 25 – 24 PENDET 17 16 9 8 TSSCTIM 10 TSFREQ TSAV 2 – 1 0 TSMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” .
• PENDET: Pen Contact Detection Enable 0: Pen contact detection disable. 1: Pen contact detection enable. When PENDET = 1, XPOS, YPOS, Z1, Z2 values of ADC_XPOSR, ADC_YPOSR, ADC_PRESSR registers are automatically cleared when PENS = 0 in ADC_ISR. • NOTSDMA: No TouchScreen DMA 0: XPOS, YPOS, Z1, Z2 are transmitted in ADC_LCDR. 1: XPOS, YPOS, Z1, Z2 are never transmitted in ADC_LCDR, therefore the buffer does not contains touchscreen values.
42.8.19 ADC Touchscreen X Position Register Name: ADC_XPOSR Address: 0xF804C0B4 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 XSCALE 19 18 11 10 XSCALE 15 – 14 – 13 – 12 – 7 6 5 4 XPOS 3 2 XPOS • XPOS: X Position The Position measured is stored here. if XPOS = 0 or XPOS = XSIZE, the pen is on the border.
42.8.20 ADC Touchscreen Y Position Register Name: ADC_YPOSR Address: 0xF804C0B8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 YSCALE 19 18 11 10 YSCALE 15 – 14 – 13 – 12 – 7 6 5 4 YPOS 3 2 YPOS • YPOS: Y Position The Position measured is stored here. if YPOS = 0 or YPOS = YSIZE, the pen is on the border.
42.8.21 ADC Touchscreen Pressure Register Name: ADC_PRESSR Address: 0xF804C0BC Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 Z2 19 18 11 10 Z2 15 – 14 – 13 – 12 – 7 6 5 4 Z1 3 2 Z1 • Z1: Data of Z1 Measurement Data Z1 necessary to calculate pen pressure. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), Z1 is tied to 0 while there is no detection of contact on the touchscreen (i.e.
42.8.
42.8.23 ADC Write Protect Mode Register Name: ADC_WPMR Address: 0xF804C0E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
42.8.24 ADC Write Protect Status Register Name: ADC_WPSR Address: 0xF804C0E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the ADC_WPSR register. 1: A Write Protect Violation has occurred since the last read of the ADC_WPSR register.
43. Synchronous Serial Controller (SSC) 43.1 Description The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
43.3 Block Diagram Figure 43-1. Block Diagram System Bus APB Bridge DMA Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 43.4 Application Block Diagram Figure 43-2.
43.5 Pin Name List Table 43-1. I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 43.6 Type Product Dependencies 43.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
43.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
43.7.1 Clock Management The transmitter clock can be generated by: an external clock received on the TK I/O pad the receiver clock the internal clock divider The receiver clock can be generated by: an external clock received on the RK I/O pad the transmitter clock the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.
43.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register.
43.7.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register.
43.7.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 920. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 922.
43.7.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 920. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 922. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR.
Figure 43-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF TD (Output) TD (Output) X BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) TD (Output) B1 STTDLY BO X B1 STTDLY TD Start = Level Change on TF (Output) Start = Any Edge on TF BO BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 43-11.
43.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. Programmable low or high levels during data transfer are supported. Programmable high levels before the start of data transfers or toggling are also supported.
43.7.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R).
Figure 43-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start Start PERIOD (1) TF/RF FSLEN TD (If FSDEN = 1) TD (If FSDEN = 0) RD Sync Data Default From SSC_TSHR From DATDEF Data Data Default From SSC_THR From SSC_THR From DATDEF Default Sync Data Data Data From SSC_THR From DATDEF Ignored Data To SSC_RHR To SSC_RHR DATLEN DATLEN STTDLY Default From DATDEF From SSC_THR Data To SSC_RSHR Sync Data Ignored Sync Data DATNB Note: 1.
43.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 43.7.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event.
43.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 43-17. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB MSB Right Channel Left Channel Figure 43-18.
Figure 43-19.
43.8.1 Write Protection Registers To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write protected by setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
43.9 Synchronous Serial Controller (SSC) User Interface Table 43-5.
43.9.1 SSC Control Register Name: SSC_CR: Address: 0xF0010000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive.
43.9.2 SSC Clock Mode Register Name: SSC_CMR Address: 0xF0010004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV.
43.9.3 SSC Receive Clock Mode Register Name: SSC_RCMR Address: 0xF0010010 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 STOP 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• START: Receive Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
43.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0xF0010014 Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 – 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
• FSOS: Receive Frame Sync Output Selection Value Name Description 0 NONE None, RF pin is an input 1 NEGATIVE Negative Pulse, RF pin is an output 2 POSITIVE Positive Pulse, RF pin is an output 3 LOW Driven Low during data transfer, RF pin is an output 4 HIGH Driven High during data transfer, RF pin is an output 5 TOGGLING Toggling at each start of data transfer, RF pin is an output • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN
43.9.5 SSC Transmit Clock Mode Register Name: SSC_TCMR Address: 0xF0010018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 – 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• START: Transmit Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data 1 RECEIVE Receive start 2 TF_LOW Detection of a low level on TF signal 3 TF_HIGH Detection of a high level on TF signal 4 TF_FALLING Detection of a falling edge on TF signal 5 TF_RISING Detection of a rising edge on TF signal 6 TF_LEVEL Detection of any level chang
43.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0xF001001C Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 FSDEN 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
• FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). Value Name Description 0 POSITIVE Positive Edge Detection 1 NEGATIVE Negative Edge Detection • FSLEN_EXT: FSLEN Field Extension Extends FSLEN field.
43.9.7 SSC Receive Holding Register Name: SSC_RHR Address: 0xF0010020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
43.9.8 SSC Transmit Holding Register Name: SSC_THR Address: 0xF0010024 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
43.9.
43.9.
43.9.11 SSC Receive Compare 0 Register Name: SSC_RC0R Address: 0xF0010038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
43.9.12 SSC Receive Compare 1 Register Name: SSC_RC1R Address: 0xF001003C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP1 7 6 5 4 CP1 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
43.9.13 SSC Status Register Name: SSC_SR Address: 0xF0010040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
• TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled. • RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled.
43.9.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0xF0010044 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt.
43.9.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0xF0010048 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt.
43.9.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0xF001004C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
43.9.17 SSC Write Protect Mode Register Name: SSC_WPMR Address: 0xF00100E4 Access: Read-write Reset: See Table 43-5 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
43.9.18 SSC Write Protect Status Register Name: SSC_WPSR Address: 0xF00100E8 Access: Read-only Reset: See Table 43-5 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register.
44. LCD Controller (LCDC) 44.1 Description The LCD controller consists of logic for transferring LCD image data from an external display buffer to an LCD module. The LCD has one display input buffer that fetches pixels through the AB master interface and a lookup table to allow palletized display configurations. The LCD controller is programmable on a per overlay basis, and supports different LCD resolution, window size, image format and pixel depth.
44.3 Block Diagram Figure 44-1.
44.4 I/O Lines Description Table 44-1. I/O Lines Description Name Description Type LCD_PWM Contrast control signal, using Pulse Width Modulation Output LCD_HSYNC Horizontal Synchronization Pulse Output LCD_VSYNC Vertical Synchronization Pulse Output LCD_DAT[23:0] LCD 24-bit data bus Output LCD_DEN Data Enable Output LCD_DISP Display Enable signal Output LCD_PCLK Pixel Clock Output 44.5 Product Dependencies 44.5.
Table 44-2. I/O Lines LCDC LCDDAT20 PC20 A LCDC LCDDAT21 PC21 A LCDC LCDDAT22 PC22 A LCDC LCDDAT23 PC23 A LCDC LCDDEN PC29 A LCDC LCDDISP PC24 A LCDC LCDHSYNC PC28 A LCDC LCDPCK PC30 A LCDC LCDPWM PC26 A LCDC LCDVSYNC PC27 A 44.5.2 Power Management The LCD Controller is not continuously clocked. The user must first enable the LCD Controller clock in the Power Management Controller before using it (PMC_PCER). 44.5.
44.6 Functional Description The LCD module integrates the following digital blocks: DMA Engine Address Generation (DEAG). This block performs data prefetch and requests access to the AHB interface. Input FIFO, stores the stream of pixels. Color Lookup Table (CLUT). These 256 RAM-based lookup table entries are selected when the color depth is set to 1, 2, 4 or 8 bpp. Output FIFO, stores the pixel prior to display. LCD Timing Engine, provides a fully programmable HSYNC-VSYNC interface.
44.6.1.4 Timing Engine Power Down Software Operation The following sequence is used to disable the display: 1. Disable the DISP signal writing DISPDIS field of the LCDC_LCDDIS register. 2. Poll DISPSTS field of the LCDC_LCDSR register to verify that the DISP is no longer activated. 3. Disable the hsync and vsync signals by writing one to SYNCDIS field of the LCDC_LCDDIS register. 4. Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is off. 5.
44.6.2.5 DMA Interrupt Generation The DMA controller operation sets the following interrupt flags in the interrupt status register CHXISR: DMA field indicates that the DMA transfer is completed. DSCR field indicates that the descriptor structure is loaded in the DMA controller. ADD field indicates that a descriptor has been added to the descriptor queue. DONE field indicates that the channel transfer has terminated and the channel is automatically disabled. 44.6.2.
44.6.3.2 Color Attributes CLUTMODE field: selects the color lookup table mode RGBMODE field: selects the RGB mode. 44.6.3.3 Window Attributes Software Operation 1. When required, write the overlay attributes configuration registers. 2. Set UPDATEEN field of the CHXCHER register. 3. Poll UPDATESR field in the CHXCHSR, the update applies when that field is reset. 44.6.4 RGB Frame Buffer Memory Bitmap 44.6.4.1 1 bpp Through Color Lookup Table Table 44-7.
44.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 Table 44-12. 16 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 16 bpp 0x2 A1[3:0] R1[3:0] 0x1 G1[3:0] 0x0 B1[3:0] A0[3:0] 8 7 6 R0[3:0] 5 4 3 G0[3:0] 2 1 0 B0[3:0] 44.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 Table 44-13.
Table 44-18. 18 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7 Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 18 bpp 0x6 R2[3:0] 0x5 G2[5:0] 0x4 8 B2[5:0] 7 6 5 4 3 R1[5:2] 2 1 0 G1[5:2] Table 44-19.
44.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:8 Table 44-25. 24 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 24 bpp 0x2 B1[7:0] 0x1 R0[7:0] 0x0 8 7 6 5 G0[7:0] 4 3 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 B0[7:0] Table 44-26.
44.6.5 Output Timing Generation 44.6.5.1 Active Display Timing Mode Figure 44-2.
Figure 44-3.
Figure 44-4.
Figure 44-5.
44.6.6 Output Format 44.6.6.1 Active Mode Output Pin Assignment Table 44-30.
44.7 LCD Controller (LCDC) User Interface Table 44-32.
Table 44-32. Register Mapping (Continued) Offset Register 0x7FC Base CLUT Register 255(1) 0x800-0x1FE4 Note: Reserved Name Access Reset – – – LCDC_ADDRSIZE Read-only 0x LCDC_BASECLUT255 0x1FEC Address Size Register 0x1FF0 IP Name1 Register LCDC_IPNAME1 Read-only 0x 0x1FF4 IP Name2 Register LCDC_IPNAME2 Read-only 0x 0x1FF8 Features Register LCDC_FEATURES Read-only 0x 0x1FFC Version Register LCDC_VERSION Read-only 0x 1. The CLUT registers are located in RAM.
44.7.1 LCD Controller Configuration Register 0 Name: LCDC_LCDCFG0 Address: 0xF8038000 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 – 14 – 6 – 13 – 5 – 12 – 4 – 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 CLKPWMSEL 10 – 2 CLKSEL 9 – 1 – 8 CGDISBASE 0 CLKPOL CLKDIV • CLKPOL: LCD Controller Clock Polarity 0: Data/Control signals are launched on the rising edge of the Pixel Clock. 1: Data/Control signals are launched on the falling edge of the Pixel Clock.
44.7.2 LCD Controller Configuration Register 1 Name: LCDC_LCDCFG1 Address: 0xF8038004 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 28 – 20 27 – 19 13 – 5 12 – 4 11 – 3 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 VSPW HSPW • HSPW: Horizontal Synchronization Pulse Width Width of the LCD_HSYNC pulse, given in pixel clock cycles. Width is (HSPW+1) LCD_PCLK cycles.
44.7.3 LCD Controller Configuration Register 2 Name: LCDC_LCDCFG2 Address: 0xF8038008 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 28 – 20 27 – 19 13 – 5 12 – 4 11 – 3 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 VBPW VFPW • VFPW: Vertical Front Porch Width This field indicates the number of lines at the end of the Frame. The blanking interval is equal to (VFPW+1) lines.
44.7.4 LCD Controller Configuration Register 3 Name: LCDC_LCDCFG3 Address: 0xF803800C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 14 – 6 13 – 5 12 – 4 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 10 – 2 9 – 1 8 – 0 HBPW HFPW • HFPW: Horizontal Front Porch Width Number of pixel clock cycles inserted at the end of the active line. The interval is equal to (HFPW+1) LCD_PCLK cycles.
44.7.5 LCD Controller Configuration Register 4 Name: LCDC_LCDCFG4 Address: 0xF8038010 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 RPF 17 24 9 PPL 1 8 16 RPF 15 – 7 14 – 6 13 – 5 12 – 4 2 0 PPL • RPF: Number of Active Rows Per Frame Number of active lines in the frame. The frame height is equal to (RPF+1) lines. • PPL: Number of Pixels Per Line Number of pixels in the frame.
44.7.
• MODE: LCD Controller Output Mode Value Name Description 0 OUTPUT_12BPP LCD output mode is set to 12 bits per pixel 1 OUTPUT_16BPP LCD output mode is set to 16 bits per pixel 2 OUTPUT_18BPP LCD output mode is set to 18 bits per pixel 3 OUTPUT_24BPP LCD output mode is set to 24 bits per pixel • VSPSU: LCD Controller Vertical Synchronization Pulse Setup Configuration 0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge.
44.7.7 LCD Controller Configuration Register 6 Name: LCDC_LCDCFG6 Address: 0xF8038018 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 7 – 6 – 5 – 28 – 20 – 12 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 PWMCVAL 4 3 PWMPOL – 2 1 PWMPS 0 • PWMPS: PWM Clock Prescaler 3-bit value. Selects the configuration of the counter prescaler module. The PWMPS field decoding is listed below.
44.7.8 LCD Controller Enable Register Name: LCDC_LCDEN Address: 0xF8038020 Access: Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 PWMEN 26 – 18 – 10 – 2 DISPEN 25 – 17 – 9 – 1 SYNCEN 24 – 16 – 8 – 0 CLKEN • CLKEN: LCD Controller Pixel Clock Enable 0: Writing this field to zero has no effect. 1: When set to one the pixel clock logical unit is activated.
44.7.9 LCD Controller Disable Register Name: LCDC_LCDDIS Address: 0xF8038024 Access: Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 PWMRST 3 PWMDIS 26 – 18 – 10 DISPRST 2 DISPDIS 25 – 17 – 9 SYNCRST 1 SYNCDIS 24 – 16 – 8 CLKRST 0 CLKDIS • CLKDIS: LCD Controller Pixel Clock Disable 0: No effect. 1: Disable the pixel clock. • SYNCDIS: LCD Controller Horizontal and Vertical Synchronization Disable 0: No effect.
44.7.10 LCD Controller Status Register Name: LCDC_LCDSR Address: 0xF8038028 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 SIPSTS 27 – 19 – 11 – 3 PWMSTS 26 – 18 – 10 – 2 DISPSTS 25 – 17 – 9 – 1 LCDSTS 24 – 16 – 8 – 0 CLKSTS • CLKSTS: Clock Status 0: Pixel Clock is disabled. 1: Pixel Clock is running. • LCDSTS: LCD Controller Synchronization status 0: Timing Engine is disabled. 1: Timing Engine is running.
44.7.11 LCD Controller Interrupt Enable Register Name: LCDC_LCDIER Address: 0xF803802C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRIE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 DISPIE 25 – 17 – 9 – 1 DISIE 24 – 16 – 8 BASEIE 0 SOFIE • SOFIE: Start of Frame Interrupt Enable Register 0: No effect. 1: Enable the interrupt. • DISIE: LCD Disable Interrupt Enable Register 0: No effect. 1: Enable the interrupt.
44.7.12 LCD Controller Interrupt Disable Register Name: LCDC_LCDIDR Address: 0xF8038030 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRID 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 DISPID 25 – 17 – 9 – 1 DISID 24 – 16 – 8 BASEID 0 SOFID • SOFID: Start of Frame Interrupt Disable Register 0: No effect. 1: Disable the interrupt. • DISID: LCD Disable Interrupt Disable Register 0: No effect. 1: Disable the interrupt.
44.7.13 LCD Controller Interrupt Mask Register Name: LCDC_LCDIMR Address: 0xF8038034 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRIM 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 DISPIM 25 – 17 – 9 – 1 DISIM 24 – 16 – 8 BASEIM 0 SOFIM • SOFIM: Start of Frame Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DISIM: LCD Disable Interrupt Mask Register 0: Interrupt source is disabled.
44.7.14 LCD Controller Interrupt Status Register Name: LCDC_LCDISR Address: 0xF8038038 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERR 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 DISP 25 – 17 – 9 – 1 DIS 24 – 16 – 8 BASE 0 SOF • SOF: Start of Frame Interrupt Status Register When set to one this flag indicates that a start of frame event has been detected. This flag is reset after a read operation.
44.7.15 Base Layer Channel Enable Register Name: LCDC_BASECHER Address: 0xF8038040 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enable the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: update windows attributes on the next start of frame.
44.7.16 Base Layer Channel Disable Register Name: LCDC_BASECHDR Address: 0xF8038044 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed.
44.7.17 Base Layer Channel Status Register Name: LCDC_BASECHSR Address: 0xF8038048 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame.
44.7.18 Base Layer Interrupt Enable Register Name: LCDC_BASEIER Address: 0xF803804C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled.
44.7.19 Base Layer Interrupt Disable Register Name: LCDC_BASEIDR Address: 0xF8038050 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled.
44.7.20 Base Layer Interrupt Mask Register Name: LCDC_BASEIMR Address: 0xF8038054 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled.
44.7.21 Base Layer Interrupt Status Register Name: LCDC_BASEISR Address: 0xF8038058 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
44.7.22 Base Layer Head Register Name: LCDC_BASEHEAD Address: 0xF803805C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor.
44.7.23 Base Layer Address Register Name: LCDC_BASEADDR Address: 0xF8038060 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer Start Address Frame buffer base address.
44.7.24 Base Layer Control Register Name: LCDC_BASECTRL Address: 0xF8038064 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled.
44.7.25 Base Layer Next Register Name: LCDC_BASENEXT Address: 0xF8038068 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address DMA Descriptor next address, this address must be word aligned.
44.7.26 Base Layer Configuration 0 Register Name: LCDC_BASECFG0 Address: 0xF803806C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 – BLEN 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 – • BLEN: AHB Burst Length Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one 32-bit data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used.
44.7.27 Base Layer Configuration 1 Register Name: LCDC_BASECFG1 Address: 0xF8038070 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 7 6 29 – 21 – 13 28 20 – 12 5 4 27 – 19 – 11 – 3 – – RGBMODE 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color lookup table is selected.
44.7.28 Base Layer Configuration 2 Register Name: LCDC_BASECFG2 Address: 0xF8038074 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
44.7.29 Base Layer Configuration 3 Register Name: LCDC_BASECFG3 Address: 0xF8038078 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the Base DMA channel is disabled. • GDEF: Green Default Default Green color when the Base DMA channel is disabled. • BDEF: Blue Default Default Blue color when the Base DMA channel is disabled.
44.7.30 Base Layer Configuration 4 Register Name: LCDC_BASECFG4 Address: 0xF803807C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 REP 1 – 24 – 16 – 8 DMA 0 – • DMA: Use DMA Data Path 0: The default color is used on the Base Layer. 1: The DMA channel retrieves the pixels stream from the memory.
44.7.31 Base CLUT Register x Register Name: LCDC_BASECLUTx [x=0..255] Address: 0xF8038400 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RCLUT GCLUT BCLUT • BCLUT: Blue Color entry This field indicates the 8 bit width Blue color of the color lookup table. • GCLUT: Green Color entry This field indicates the 8 bit width Green color of the color lookup table.
45. Advanced Encryption Standard (AES) 45.1 Description The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-38A Recommendation.
45.4 Functional Description The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext.
45.4.3 Start Modes The SMOD field in the AES_MR allows selection of the encryption (or decryption) start mode. 45.4.3.1 Manual Mode The sequence order is as follows: Write the AES_MR with all required fields, including but not limited to SMOD and OPMOD. Write the 128-bit/192-bit/256-bit key in the Key Registers (AES_KEYWRx). Write the initialization vector (or counter) in the Initialization Vector Registers (AES_IVRx). Note: The Initialization Vector Registers concern all modes except ECB.
When writing data to AES with a first DMA channel, data are first fetched from a memory buffer (source data). It is recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination data size depends on the mode of operation. When reading data from the AES with the second DMA channel, the source data is the data read from AES and data destination is the memory buffer.
If LOD = 1 The DATRDY flag is cleared when at least one Input Data Register is written, so before the start of a new transfer (See Figure 45-2). No more Output Data Register reads are necessary between consecutive encryptions/decryptions. Figure 45-2. Manual and Auto Modes with LOD = 1 Write START bit in AES_CR (Manual mode) or Write AES_IDATARx register(s) (Auto mode) Write AES_IDATARx register(s) DATRDY Encryption or Decryption Process 45.4.4.
Figure 45-4. DMA transfer with LOD = 1 Enable DMA Channels associated with TDES_IDATARx and TDES_ODATARx registers Multiple Encryption or Decryption Processes Write accesses into AES_IDATARx BTC / channel 0 DATRDY Message fully transferred Message fully processed (cipher or decipher) MAC result can be read Table 45-4 summarizes the different cases. Table 45-4.
45.5 Security Features 45.5.1 Unspecified Register Access Detection When an unspecified register access occurs, the URAD bit in the Interrupt Status Register (AES_ISR) raises. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field.
45.6 Advanced Encryption Standard (AES) User Interface Table 45-5.
45.6.1 AES Control Register Name: AES_CR Address: 0xF000C000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – – – – – START • START: Start Processing 0: No effect 1: Starts manual encryption/decryption process. • SWRST: Software Reset 0: No effect. 1: Resets the AES.
45.6.2 AES Mode Register Name: AES_MR Address: 0xF000C004 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 CKEY 15 – 14 13 LOD 12 11 OPMOD 7 6 5 CFBS 10 9 KEYSIZE 4 PROCDLY 8 SMOD 3 2 1 0 DUALBUFF – – CIPHER • CIPHER: Processing Mode 0: Decrypts data. 1: Encrypts data. • DUALBUFF: Dual Input Buffer Value Name Description 0x0 INACTIVE AES_IDATARx cannot be written during processing of previous block.
• OPMOD: Operation Mode Value Name Description 0x0 ECB ECB: Electronic Code Book mode 0x1 CBC CBC: Cipher Block Chaining mode 0x2 OFB OFB: Output Feedback mode 0x3 CFB CFB: Cipher Feedback mode 0x4 CTR CTR: Counter mode (16-bit internal counter) Values which are not listed in the table must be considered as “reserved”. For CBC-MAC operating mode, please set OPMOD to CBC and LOD to 1. • LOD: Last Output Data Mode 0: No effect.
45.6.3 AES Interrupt Enable Register Name: AES_IER Address: 0xF000C010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
45.6.4 AES Interrupt Disable Register Name: AES_IDR Address: 0xF000C014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
45.6.5 AES Interrupt Mask Register Name: AES_IMR Address: 0xF000C018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
45.6.6 AES Interrupt Status Register Name: AES_ISR Address: 0xF000C01C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data not valid. 1: Encryption or decryption process is completed.
45.6.7 AES Key Word Register x Name: AES_KEYWRx Address: 0xF000C020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEYW 23 22 21 20 KEYW 15 14 13 12 KEYW 7 6 5 4 KEYW • KEYW: Key Word The four/six/eight 32-bit Key Word registers set the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption. AES_KEYWR0 corresponds to the first word of the key and respectively AES_KEYWR3/AES_KEYWR5/AES_KEYWR7 to the last one.
45.6.8 AES Input Data Register x Name: AES_IDATARx Address: 0xF000C040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA • IDATA: Input Data Word The four 32-bit Input Data registers set the 128-bit data block used for encryption/decryption. AES_IDATAR0 corresponds to the first word of the data to be encrypted/decrypted, and AES_IDATAR3 to the last one.
45.6.9 AES Output Data Register x Name: AES_ODATARx Address: 0xF000C050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The four 32-bit Output Data registers contain the 128-bit data block that has been encrypted/decrypted. AES_ODATAR0 corresponds to the first word, AES_ODATAR3 to the last one.
45.6.10 AES Initialization Vector Register x Name: AES_IVRx Address: 0xF000C060 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IV 23 22 21 20 IV 15 14 13 12 IV 7 6 5 4 IV • IV: Initialization Vector The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input.
46. Secure Hash Algorithm (SHA) 46.1 Description The Secure Hash Algorithm (SHA) is compliant with the American FIPS (Federal Information Processing Standard) Publication 180-2 specification. The 512-bit block of message is respectively stored in 16 x 32-bit registers (SHA_IDATARx/SHA_ODATARx) which are all write-only. As soon as the input data is written, the hash processing may be started. The registers comprising the block of a padded message must be entered consecutively.
46.4 Functional Description The Secure Hash Algorithm (SHA) module requires a padded message according to FIPS180-2 specification. The first block of the message must be indicated to the module by a specific command. The SHA module produces a N-bit message digest each time a block is written and processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for SHA256. 46.4.1 SHA Algorithm The module can process SHA1, SHA224, SHA256, by means of a configuration field in the SHA_MR register. 46.4.
46.4.4.2 Auto Mode Auto Mode is similar to Manual Mode, except that in this mode, as soon as the correct number of Input Data Registers is written, processing is automatically started without any action in the control register. 46.4.4.3 DMA Mode The DMA can be used in association with the SHA to perform the algorithm on a complete message without any action by the software during processing. The SMOD field of the SHA_MR must be set to 0x2. The DMA must be configured with non incremental addresses.
Let’s assume the message is received through a serial to parallel communication channel, the first received character is 0xca and stored at first memory location (initial offset), second octet being 0xfe is stored at initial offset + 1. When reading on a 32-bit Little Endian system bus, the first word read back from system memory is 0x_dede_feca. When the SHA_ODATAxR registers are read, the hash result is organized in Little Endian format, allowing system memory storage in the same format as the message.
46.5 Secure Hash Algorithm (SHA) User Interface Table 46-2. Register Mapping Offset Register Name Access Reset 0x00 Control Register SHA_CR Write-only – 0x04 Mode Register SHA_MR Read-write 0x0000100 0x08-0x0C Reserved – – – 0x10 Interrupt Enable Register SHA_IER Write-only – 0x14 Interrupt Disable Register SHA_IDR Write-only – 0x18 Interrupt Mask Register SHA_IMR Read-only 0x0 0x1C Interrupt Status Register SHA_ISR Read-only 0x0 0x20-0x3C 0x40 ...
46.5.
46.5.
46.5.3 SHA Interrupt Enable Register Name: SHA_IER Address: 0xF0014010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Enable • URAD: Unspecified Register Access Detection Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
46.5.4 SHA Interrupt Disable Register Name: SHA_IDR Address: 0xF0014014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Disable • URAD: Unspecified Register Access Detection Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
46.5.5 SHA Interrupt Mask Register Name: SHA_IMR Address: 0xF0014018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Mask • URAD: Unspecified Register Access Detection Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
46.5.6 SHA Interrupt Status Register Name: SHA_ISR Address: 0xF001401C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data is not valid. 1: 512-bit block process is completed.
46.5.7 SHA Input Data x Register Name: SHA_IDATARx [x=0..15] Address: 0xF0014040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA • IDATA: Input Data The 32-bit Input Data registers allow to load the data block used for hash processing. These registers are write-only to prevent the input data from being read by another application.
46.5.8 SHA Output Data x Register Name: SHA_ODATARx [x=0..15] Address: 0xF0014080 Access: Read only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data These registers can be used to read the resulting message digest . When SHA processing is in progress, these registers return 0x0000.
47. True Random Number Generator (TRNG) 47.1 Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3. 47.2 47.
47.5 Functional Description As soon as the TRNG is enabled in the control register (TRNG_CR), the generator provides one 32-bit value every 84 clock cycles. Interrupt trng_int can be enabled in the TRNG_IER (respectively disabled in the TRNG_IDR). This interrupt is set when a new random value is available and is cleared when the status register (TRNG_ISR) is read. The flag DATRDY of the (TRNG_ISR) is set when the random data is ready to be read out on the 32-bit output data register (TRNG_ODATA).
47.6 True Random Number Generator (TRNG) User Interface Table 47-2.
47.6.1 TRNG Control Register Name: TRNG_CR Address: 0xF8048000 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – ENABLE • ENABLE: Enables the TRNG to provide random values 0: Disables the TRNG. 1: Enables the TRNG if 0x524E47 (“RNG” in ASCII) is written in KEY field at the same time. • KEY: Security Key.
47.6.2 TRNG Interrupt Enable Register Name: TRNG_IER Address: 0xF8048010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
47.6.3 TRNG Interrupt Disable Register Name: TRNG_IDR Address: 0xF8048014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
47.6.4 TRNG Interrupt Mask Register Name: TRNG_IMR Address: 0xF8048018 Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
47.6.5 TRNG Interrupt Status Register Name: TRNG_ISR Address: 0xF804801C Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data is not valid or TRNG is disabled. 1: New Random value is completed. The DATRDY bit is cleared when this register is read.
47.6.6 TRNG Output Data Register Name: TRNG_ODATA Address: 0xF8048050 Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The 32-bit Output Data register contains the 32-bit random data.
48. Electrical Characteristics 48.1 Absolute Maximum Ratings Table 48-1. Absolute Maximum Ratings* Junction Temperature..................................................125°C *NOTICE: Storage Temperature..................................-60°C to +150°C Voltage on Input Pins with Respect to Ground.....-0.3V to VDDIO+0.3V(+ 4V max) Maximum Operating Voltage (VDDCORE and VDDPLL) ...........................................1.
Table 48-2. DC Characteristics (Continued) VOL VOH Output Low-level Voltage Output High-level Voltage VT- Schmitt trigger Negative going threshold Voltage VT+ Schmitt trigger Positive going threshold Voltage VHYS Schmitt trigger Hysteresis RPULLUP IO Pull-up Resistance Output Current IO Max, VVDDIO from 3.0V to 3.6V 0.4 V CMOS (IO <0.3 mA), VVDDIO from 1.65V to 1.95V 0.1 V TTL (IO Max), VVDDIO from 1.65V to 1.95V 0.4 V IO Max, VVDDIO from 3.0V to 3.6V VVDDIO - 0.4 V CMOS (IO <0.
48.3 Power Consumption Typical power consumption of PLLs, Slow Clock and Main Oscillator. Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup. Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 48.3.
Table 48-4. Power Consumption by Peripheral in Active Mode Peripheral 48.4 Consumption PIO Controller 6 USART 6 ADC 5 TWI 2 SPI 3 UART 3 UHP 5 UDP 5 LCDC 3 PWM 6 HSMCI 3 SSC 5 Timer Counter Channels 12 DMA 1 AES 4 SHA 3 TRNG 1 Unit µA/MHz Clock Characteristics 48.4.1 Processor Clock Table 48-5.
48.4.3 Main Oscillator Characteristics Table 48-7. Main Oscillator Characteristics Symbol Parameter 1/(tCPMAIN) CCRYSTAL CINT(1) CLEXT (1) Conditions Crystal Oscillator Frequency Crystal Load Capacitance Typ Max Unit 8 16 20 MHz 17.5 pF 2.35 pF 12.5 Internal Load Capacitance External Load Capacitance Min 1.85 2.1 (1) 20.8 pF (1) 30.8 pF CCRYSTAL = 12.5 pF CCRYSTAL = 17.
48.4.4 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. Table 48-8. Crystal Characteristics Symbol ESR Parameter Equivalent Series Resistor Rs Conditions Min Typ Max fundamental @3MHz 200 fundamental @8MHz 100 fundamental @16MHz 80 fundamental @20MHz 50 Unit Ω CM Motional Capacitance 8 fF CS Shunt Capacitance 7 pF 48.4.
48.5 12 MHz RC Oscillator Characteristics Table 48-10. 12 MHz RC Oscillator Characteristics Symbol Parameter F0 Min Typ Max Units Nominal Frequency 8.4 12 15.6 MHz Duty Duty Cycle 45 50 55 % IDD ON Power Consumption Oscillation 86 140 86 125 tON Start-up time 6 10 µs IDD STDBY Standby consumption 22 µA 48.6 Conditions µA 32 kHz Oscillator Characteristics Table 48-11.
48.6.1 32 kHz Crystal Characteristics Table 48-12. 32 kHz Crystal Characteristics Symbol Parameter Conditions Min ESR Equivalent Series Resistor Rs Crystal @ 32.768 kHz CM Motional Capacitance Crystal @ 32.768 kHz CS Shunt Capacitance Crystal @ 32.768 kHz Current dissipation Unit 50 100 kΩ 0.6 3 fF 0.6 2 pF CCRYSTAL32 = 6 pF 0.55 1.3 µA (1) CCRYSTAL32 = 12.5pF 0.85 1.6 µA RS = 50 kΩ (1) CCRYSTAL32 = 6 pF 0.7 2.0 µA (1) CCRYSTAL32 = 12.5 pF 1.1 2.2 µA 0.
48.8 PLL Characteristics Table 48-15. PLLA Characteristics Symbol Parameter Conditions Min FOUT Output Frequency Refer to following table FIN Input Frequency IPLL Current Consumption T Startup Time Typ Max Unit 400 800 MHz 2 32 MHz 4.5 mA 1 µA 50 µs active mode 3.6 standby mode The following configuration of ICPLLA and OUTA must be done for each PLLA frequency range. Table 48-16. PLLA Frequency Regarding ICPLLA and OUTA 48.
48.10 Analog-to-Digital Converter (ADC) Table 48-18. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency 10-bit resolution mode Startup Time Return from Idle Mode Track and Hold Acquisition Time (TTH) Conversion Time (TCT) Throughput Rate Note: Min ADC Clock = 13.2 MHz (1) ADC Clock = 13.2 MHz (1) ADC Clock = 5 MHz Typ Units 13.2 MHz 40 µs 0.5 µs 1.74 (1) µs 4.6 ADC Clock = 13.2 MHz(1) ADC Clock = 5 MHz Max 440 (1) kSPS 192 1.
Table 48-21. Transfer Characteristics Parameter Min Resolution Typ Max 10 Integral Non-linearity Units bit ±2 LSB ±2 LSB Differential Non-linearity - ADC Clock = 13.2 MHz - ADC Clock = 5 MHz ±0.9 Offset Error ±10 mV - ADC Clock = 13.2 MHz ±3 LSB - ADC Clock = 5 MHz ±2 Gain Error 48.11 USB Transceiver Characteristics 48.11.1 Electrical Characteristics Table 48-22. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit 0.
48.12 Core Power Supply POR Characteristics Table 48-23. Power-On-Reset Characteristics Symbol Parameter Conditions Min Typ Max Units Vth+ Threshold Voltage Rising Minimum Slope of +2.0V/30ms 0.5 0.7 0.89 V Vth- Threshold Voltage Falling 0.4 0.6 0.85 V TRES Reset Time 30 70 130 µs Idd Current consumption 3 7 µA After TRES 48.12.1 Power Sequence Requirements The AT91 board design must comply with the power-up guidelines below to guarantee reliable operation of the device.
The TSLCK min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz). TRES = 30 µs T1 = 66 µs T2 = 352 µs VDDPLL is to be established prior to VDDCORE to ensure the PLL is powered once enabled into the ROM code. As a conclusion, establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE at last, to ensure a reliable operation of the device. 48.13 SMC Timings 48.13.
48.13.2.2 Read Timings Table 48-26. SMC Read Signals - NRD Controlled (READ_MODE= 1) Symbol Parameter Min VDDIOM supply Units 1.8V 3.3V NO HOLD SETTINGS (nrd hold = 0) SMC1 Data Setup before NRD High SMC2 Data Hold after NRD High 13.7 11.8 ns 0 0 ns 10.7 8.8 ns 0 0 ns (nrd setup + nrd pulse)* tCPMCK 5.3 (nrd setup + nrd pulse)* tCPMCK - 5.1 ns (nrd setup + nrd pulse - ncs rd setup) * tCPMCK -4.8 (nrd setup + nrd pulse ncs rd setup) * tCPMCK - 4.9 ns nrd pulse * tCPMCK - 3.
48.13.2.3 Write Timings Table 48-28. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Symbol Parameter Min 1.8V Supply 3.3V Supply Units HOLD or NO HOLD SETTINGS (nwe hold ≠ 0, nwe hold = 0) SMC15 Data Out Valid before NWE High nwe pulse * tCPMCK - 4.1 nwe pulse * tCPMCK - 4.0 ns SMC16 NWE Pulse Width nwe pulse * tCPMCK - 3.0 nwe pulse * tCPMCK - 3.1 ns SMC17 NBS0/A0 NBS1, NBS2/A1, NBS3, A2 A25 valid before NWE low nwe setup * tCPMCK - 4.2 nwe setup * tCPMCK - 4.
Figure 48-5. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0/A1/NBS[3:0] /A2-A25 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC9 SMC8 SMC23 SMC10 SMC11 SMC22 SMC26 D0 - D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD NCS Controlled READ with HOLD NCS Controlled WRITE Figure 48-6.
48.14 DDRSDRC Timings The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules. DDR2, LP-DDR and SDR timings are specified by the JEDEC standard. Supported speed grade limitations: DDR2-400 limited at 133 MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#) LP-DDR (1.8V, 30pF on data/control, 10pF on CK) Tcyc = 5.0 ns, Fmax = 125 MHz Tcyc = 6.0 ns, Fmax = 110 MHz Tcyc = 7.5 ns, Fmax = 95 MHz SDR-100 (3.
48.15.1.2 Timing Conditions Timings are given assuming a capacitance load on MISO, SPCK and MOSI: Table 48-30. Capacitance Load for MISO, SPCK and MOSI (product dependent) Corner Supply MAX MIN 3.3V 40 pF 5 pF 1.8V 20 pF 5 pF 48.15.1.3 Timing Extraction Figure 48-7. SPI Master mode 1 and 2 SPCK SPI0 SPI1 MISO SPI2 MOSI Figure 48-8.
Figure 48-9. SPI Slave mode 0 and 3 NPCS0 SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 48-10. SPI Slave mode 1 and 2 NPCS0 SPI13 SPI12 SPCK SPI9 MISO SPI10 SPI11 MOSI Figure 48-11.
Table 48-31. SPI Timings with 3.3V Peripheral Supply Symbol Parameter Cond Min Max Units 66 MHz Master Mode SPISPCK SPI Clock SPI0 MISO Setup time before SPCK rises SPI1 13.7 ns MISO Hold time after SPCK rises 0 ns SPI2 SPCK rising to MOSI 0 SPI3 MISO Setup time before SPCK falls SPI4 SPI5 7.6 ns 13.2 ns MISO Hold time after SPCK falls 0 ns SPCK falling to MOSI 0 7.7 ns 14.1 ns Slave Mode SPI6 SPCK falling to MISO 2.7 SPI7 MOSI Setup time before SPCK rises 2.
Table 48-32. SPI Timings with 1.8V Peripheral Supply Symbol Parameter Cond Min Max SPI10 MOSI Setup time before SPCK falls 2.4 ns SPI11 MOSI Hold time after SPCK falls 0.7 ns SPI12 NPCS0 setup to SPCK rising 4.5 ns SPI13 NPCS0 hold after SPCK falling 0 ns SPI14 NPCS0 setup to SPCK falling 3.9 ns SPI15 NPCS0 hold after SPCK rising 0 ns SPI16 NPCS0 falling to MISO valid 17.3 Units ns Figure 48-12.
48.15.2.2 Timing Extraction Figure 48-13. SSC Transmitter, TK and TF in output TK (CKI =0) TK (CKI =1) SSC0 TF/TD Figure 48-14. SSC Transmitter, TK in input and TF in output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 48-15.
Figure 48-16. SSC Transmitter, TK and TF in input TK (CKI=1) TK (CKI=0) SSC5 SSC6 TF SSC7 TD Figure 48-17. SSC Receiver RK and RF in input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 48-18.
Figure 48-19. SSC Receiver, RK and RF in output RK (CKI=1) RK (CKI=0) SSC12 SSC11 RD SSC13 RF Figure 48-20. SSC Receiver, RK in output and RF in input RK (CKI=0) RK (CKI=1) SSC12 SSC11 RF/RD Table 48-34. SSC Timings Symbol Parameter Conditions Min Max 1.8V domain(3) 2.1 13.5 (4) 2.1 13.2 1.8V domain(3) 2.8 15.4 (4) 2.1 11.
Table 48-34. SSC Timings Symbol SSC7(1)(2) Parameter Conditions TK edge to TF/TD (TK input, TF input) Min Max 1.8V domain (3) 2.8 (+3*tCPMCK) 15.4(+3*tCPMCK) 3.3V domain (4) 2.1 (+3*tCPMCK) 11.
48.15.3 HSMCI The High Speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1. 48.15.4 USART in SPI Mode Timings 48.15.4.1 Timing conditions Timings are given assuming a capacitance load on Table 48-33. Table 48-35. Capacitance Load Corner Supply MAX MIN 3.3V 40pF 5 pF 1.8V 20pF 5 pF 48.15.4.2 Timing extraction Figure 48-22.
Figure 48-24. USART SPI Slave mode: (Mode 0 or 3) NSS SPI14 SPI15 SCK SPI9 MISO SPI10 SPI11 MOSI Table 48-36. USART SPI Timings Symbol Parameter Conditions Min Max Units Master Mode SPI0 SCK Period SPI1 Input Data Setup Time SPI2 Input Data Hold Time SPI3 Chip Select Active to Serial Clock SPI4 Output Data Setup Time SPI5 Serial Clock to Chip Select Inactive 1.8v domain(1) 3.3v domain(2) MCK/6 ns 1.8v domain(1) 0.5 * MCK + 3.5 (2) 0.5 * MCK + 3.3 1.8v domain(1) 1.
Table 48-36. USART SPI Timings (Continued) Symbol Parameter Conditions SPI10 MOSI Setup time before SCK falls SPI11 MOSI Hold time after SCK falls SPI12 NPCS0 setup to SCK rising SPI13 NPCS0 hold after SCK falling SPI14 NPCS0 setup to SCK falling SPI15 NPCS0 hold after SCK rising Min 1.8v domain (1) 2 * MCK + 2.6 3.3v domain (2) 2 * MCK + 2.4 1.8v domain(1) 1.5 (2) 1.2 3.3v domain 1.8v domain(1) 2.5 * MCK + 1.4 (2) 2.5 * MCK + 1.1 1.8v domain(1) 1.5 * MCK + 2.4 (2) 1.
49. Mechanical Overview of the 217-ball and 247-ball BGA Packages 49.1 217-ball BGA Package Figure 49-1. 217-ball BGA Package Drawing Table 49-1. Ball Information Ball pitch 0.8 mm +/- 0.05 Ball Diameter 0.4 mm +/- 0.
Table 49-2. Soldering Information Ball Land 0.43 mm +/- 0.05 Solder Mask Opening 0.30 mm +/- 0.05 Table 49-3. Device and 217-ball BGA Package Maximum Weight 450 mg Table 49-4. 217-ball BGA Package Characteristics Moisture Sensitivity Level 3 Table 49-5.
49.2 247-ball BGA Package Figure 49-2.
Table 49-6. Ball Information Ball pitch 0.5 mm +/- 0.05 Ball Diameter 0.3 mm +/- 0.05 Table 49-7. Soldering Information Ball Land 0.35 mm +/- 0.05 Solder Mask Opening 0.27 mm +/- 0.05 Table 49-8. Device and 247-ball BGA Package Maximum Weight 177 mg Table 49-9. 247-ball BGA Package Characteristics Moisture Sensitivity Level 3 Table 49-10. Package Reference JEDEC Drawing Reference none JESD97 Classification e1 49.3 Marking All devices are marked with the Atmel logo and the ordering code.
50. SAM9N12/SAM9CN11/SAM9CN12 Ordering Information Table 50-1.
51. SAM9N/CN Series Errata 51.1 SAM9N12/CN11/CN12 Errata 51.1.1 Reset Controller (RSTC) 51.1.1.1 RSTC: Reset during SDRAM Accesses When a Reset (User reset, watchdog, software reset) occurs during SDRAM read access, the SDRAM clock is turned off while data is ready to be read on the data bus. The SDRAM maintains the data until the clock restarts.
51.2 SAM9CN12 Errata: Revision A 51.2.1 BootROM 51.2.1.1 Boot from SPI Serial Flash Devices (xx25xxx) Is not Working The boot from SPI serial Flash series is not working. SAM9CN12 supports only booting from AT45 DataFlash series. Problem Fix/Workaround AT45 DataFlash series must be used. Please use one of the following Data/Serial Flashes: AT45DB321, AT45DB642. 51.2.2 16 MHz Main Crystal 51.2.2.
Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during document review and approval loop. Doc Revision 11063K Doc. Rev 11063J Change Request Ref. Comments Section 51. ”SAM9N/CN Series Errata” Section 51.3 ”SAM9CN12 Errata: Revision B”: Section 51.3.1.1 ”Boot from SPI Data/Serial Flash Devices do not work with All Memories”: Corrected data/serial Flash reference from AT25DF012 to AT25DF021 9429 Deleted Section 51.3.
Doc. Rev 11063J Comments Change Request Ref. RTC: Updated Section 15.2 ”Embedded Characteristics”. 8544 Section 15.5.3 ”Alarm”, added a paragraph on SECEN, MINEN, HOUREN enabling with the corresponding note. 8900/ 9027 Added the same note in Section 15.6.5 ”RTC Time Alarm Register” and Section 15.6.6 ”RTC Calendar Alarm Register”. WDT: Updated Section 17.1 ”Description”. 8429 Section 17.2 ”Embedded Characteristics”, added the 2nd bullet and removed AMBA references. Section 17.
Doc. Rev 11063J Comments Change Request Ref. PIO: Section 23.2 ”Embedded Characteristics”, removed a bullet on configuration lock. 8909 Section 23.4.4 ”Interrupt Generation”, revised content in the 1st paragraph. 8324 Section 23.5 ”Functional Description”: - added pull-down resistor and the corresponding registers in Figure 23-3, "I/O Line Control Logic" 8522 - Section 23.5.14 ”Register Write Protection”: - changed the section title and revised the content rfo Section 23.
Doc. Rev 11063J Comments Change Request Ref. PMECC: Section 28.2 ”Embedded Characteristics”, added a line on supporting 8-bit Nand Flash data bus. Section 28.6.11 ”PMECC Interrupt Status Register”, fixed a typo in the register table: 8403 - replaced duplicate bits 31 - 24 by missing 7 - 0 SMC: Replaced ‘turned out’ with ‘switched to output mode ‘ in Section 30.9.4.1 ”Write is Controlled by NWE (WRITE_MODE = 1)” and Section 30.9.4.2 ”Write is Controlled by NCS (WRITE_MODE = 0)”.
Doc. Rev 11063J Comments Change Request Ref. HSMCI: Section 35.8 ”High Speed MultiMedia Card Operations”: 9012 - corrected HSMCI_MR to HSMCI_BLKR when referring to Block Length field that is not available in HSMCI_MR and removed Note 2 in Figure 35-8, "Read Functional Flow Diagram" and Figure 35-9, "Write Functional Flow Diagram" Section 35.8.1 ”Command - Response Operation”: rfo - reorganized table content in ALL_SEND_CID command example to eliminate empty cells in header row Section 35.
Doc. Rev 11063J Comments Change Request Ref. TC: Section 37.7 ”Timer Counter (TC) User Interface”: rfo - changed the order of register description sections to match Table 37-5 ”Register Mapping” Section 37.7.2 ”TC Channel Mode Register: Capture Mode”: 9107 - TCCLKS: added details for values 0 - 4 in the bitfield description table Section 37.7.
Doc. Rev 11063J Comments Change Request Ref. Section 39.11 ”Write Protection System”: 8845 - replaced the acronym of the TWI Write Protection Status register with a cross-reference to the corresponding section (the acronym changed: TWI_WPROT_STATUS --> TWI_WPSR) - renamed bitfields of the write protection registers (WPROTERR --> WPVSRC, WPROTADDR --> WPVSRC, SECURITY_CODE --> WPKEY) Section 39.
Doc. Rev 11063J Comments Change Request Ref. - Section 40.8.24 ”USART IrDA FILTER Register”: 8508 - IRDA_FILTER: replaced the bitfield description with a new content including IRDA_FILTER programming criteria - Section 40.8.29 ”USART Write Protect Mode Register”: 8791 - WPKEY: replaced the bitfield description with a table UART: Section 41.2 ”Embedded Characteristics”, removed a redundant bullet on UART compatible features 8326 Section 41.4.
Doc. Rev 11063J Comments Change Request Ref. AES: Section 45.6.2 ”AES Mode Register”: 8859 - CKEY: replaced the bitfield description with a table 8892 Section 45.6.10 ”AES Initialization Vector Register x”: - IV: added details on CBC, OFB, CFB, and CTR modes in the bitfield description SHA: Section 46.5 ”Secure Hash Algorithm (SHA) User Interface”: 8216 - Table 46-2 ”Register Mapping”: changed the reset value for SHA_MR from 0x1 to 0x0000100 TRNG: Added new sections: - Section 47.
Doc. Rev 11063I Comments Change Request Ref. PMC: Note added in MAINFRDY field in Section 22.12.8 “PMC Clock Generator Main Clock Frequency Register”. 8870 DMAC: Text updated in Section 32.1 “Description”, Section 32.2 “Embedded Characteristics”, Section 32.5.4.3 “Ending Multi-buffer Transfers”, Section 32.6 “DMAC Software Requirements”. 8441 Ordering Information: In Table 50-1, “SAM9N12/CN11/CN12 Ordering Information”, BGA247 package ordering codes added. 8804 Errata: Doc. Rev 11063H Section 51.
Doc. Rev 11063G Comments Change Request Ref. Overview: Added “Write Protected Registers in Section 1. “Features”. 8213 Product name updated to SAM9N12/SAM9CN11/SAM9CN12. 8244 “Description” updated with the various devices configurations. Bullets for SAM9CN11 and SAM9N12 added in Section 7.3 “Chip Identification”. Boot Strategies: Boot Strategy from SAM9CN12 removed to create the separate Secure Boot document, and replaced by the previous Boot Strategies from SAM9N12.
Doc. Rev 11063F Comments Change Request Ref. Description: Section “Description”, 125 MHz --> 133 MHz 7928 “FIPS PUB 46-3 compliant TDES” removed from 3rd paragraph rfo Signal Description: rfo Table 3-1, “Signal Description List”, NFD0-NFD16 --> NFD0-NFD15 Power Considerations: Section 5.2 Programmable I/O Lines Power Supplies and Current Drive removed from Section 5. “Power Considerations”, as the same contents already exists in Section 27.7.
Doc. Rev 11063E Comments Change Request Ref. Overview: “Description”, updated...”Processor running up to 400 MHz...” 7847 updated...”System running up to 133 MHz...” DDRSDRC: 7891 Former Section 29.7 “Programmable IO Delays” removed from datasheet. PIO: Section 23.5.11 “Programmable I/O Delays”, “Only PADs PA[15:11] and PA[20:18] can be configured.” 7886 Section 23.5.12 “Programmable I/O Drive”, “It is possible to configure the I/O drive for pads PA[31:0], PB[18:0] and PC[31:0].” PMC: Section 21.
Doc. Rev Comments 11063C Change Request Ref. Overview: “Description” SLC NAND Flash is supported. rfo Section “Description”, 1st paragraph, the 2nd sentence was removed. Table 4-1, “BGA217 Pin Description”, table updated with values in Ball column. Table 5-1, “SAM9N12/CN11/CN12 Power Supplies”, VDDFUSE Voltage Range updated, 3.0V-3.6V. 7395 Section 6.3.3 “DDR-SDRAM Controller”, revised. rfo Section 7.3 “Chip Identification”, removed “two” lines. 7269 Section 8.
Doc. Rev Comments (Continued) 11063C Change Request Ref. HSMCI: Table 35-8, “Register Mapping” and Section 35.14.20 “HSMCI FIFOx Memory Aperture”, HSMCI_FIFOx offset 7253 updated. MATRIX: Section 26-5 “Chip Configuration User Interface”, CCFG_EBICSA offset values revised.
Doc. Rev Comments (Continued) 11063C Change Request Ref. UDP: Section 33.4 “Product Dependencies”, second paragraph removed. Section 33.5 “Typical Connection”, revised schematic and VBUS Monitoring. 7322 Section 33.6.3.2 “Entering Attached State”, revised, replaced paragraphs before Warning. Section 33.7.12 “UDP Transceiver Control Register”, bit field 9 is dedicated to PUON. UHP: Section 34-1 “Block Diagram”, removed Warning. 7322 Section 34.6 “Typical Connection”, revised schematic and text.
Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . .
10.5 10.6 Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11. Advanced Interrupt Controller (AIC) . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics .
17.5 Watchdog Timer (WDT) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 18. Shutdown Controller (SHDWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24. Debug Unit (DBGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 24.1 24.2 24.3 24.4 24.5 24.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . .
30. Static Memory Controller (SMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 371 30.1 30.2 30.3 30.4 30.5 30.6 30.7 30.8 30.9 30.10 30.11 30.12 30.13 30.14 30.15 30.16 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34.6 Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 35. High Speed MultiMedia Card Interface (HSMCI) . . . . . . . . . . . . . . 561 35.1 35.2 35.3 35.4 35.5 35.6 35.7 35.8 35.9 35.10 35.11 35.12 35.13 35.14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . .
39.6 39.7 39.8 39.9 39.10 39.11 39.12 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode . . . . . . . . . . . . . . . . . . .
44.3 44.4 44.5 44.6 44.7 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller (LCDC) User Interface . . . . . . . . . . . . .
50. SAM9N12/SAM9CN11/SAM9CN12 Ordering Information . . . . . . 1076 51. SAM9N/CN Series Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 51.1 51.2 51.3 SAM9N12/CN11/CN12 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 SAM9CN12 Errata: Revision A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 SAM9CN12 Errata: Revision B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 Revision History . . . . . . . . .
Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.
