User manual

Programmer’s Model

• the RR bit.

Assuming that TCM regions are disabled, the caches behave as shown in Table 2-12.

If either the DCache or the ICache is disabled, then the contents of that cache are not

accessed. If the cache is subsequently re-enabled, the contents will not have changed.

To guarantee that memory coherency is maintained, the DCache must be cleaned of

dirty data before it is disabled.

Table 2-12 Effects of Control Register on caches

Cache MMU Behavior

ICache disabled Enabled or

disabled

All instruction fetches are from external memory (AHB).

ICache enabled Disabled All instruction fetches are cachable, with no protection checks. All addresses are flat

mapped. That is VA = MVA = PA.

ICache enabled Enabled Instruction fetches are cachable or noncachable, and protection checks are performed.

All addresses are remapped from VA to PA, depending on the MMU page table entry.

That is, VA translated to MVA, MVA remapped to PA.

DCache disabled Enabled or

disabled

All data accesses are to external memory (AHB).

DCache enabled Disabled All data accesses are noncachable nonbufferable. All addresses are flat mapped. That

is VA = MVA = PA.

DCache enabled Enabled All data accesses are cachable or noncachable, and protection checks are performed.

All addresses are remapped from VA to PA, depending on the MMU page table entry.

That is, VA translated to MVA, MVA remapped to PA.