User manual

Glossary

TAP See Test access port.

TCM See Tightly coupled memory.

Test Access Port (TAP)

The collection of four mandatory and one optional terminals that form the input/output

and control interface to a JTAG boundary-scan architecture. The mandatory terminals

are TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is

mandatory in ARM cores because it is used to reset the debug logic.

Thumb instruction A halfword that specifies an operation for an ARM processor in Thumb state to

perform. Thumb instructions must be halfword-aligned.

Thumb state A processor that is executing Thumb (16-bit) halfword aligned instructions is operating

in Thumb state.

Tightly coupled memory (TCM)

An area of low latency memory that provides predictable instruction execution or data

load timing in cases where deterministic performance is required. TCMs are suited to

holding:

- critical routines (such as for interrupt handling)

- scratchpad data

- data types whose locality is not suited to caching

- critical data structures (such as interrupt stacks).

TLB See Translation Look-aside Buffer.

Translation Lookaside Buffer (TLB)

A cache of recently used page table entries that avoid the overhead of page table

walking on every memory access. Part of the Memory Management Unit.

Translation table A table, held in memory, that contains data that defines the properties of memory areas

of various fixed sizes.

Translation table walk

The process of doing a full translation table lookup. It is performed automatically by

hardware.

Undefined Indicates an instruction that generates an Undefined instruction trap. See the ARM

Architecture Reference Manual for more details on ARM exceptions.

Unpredictable Means that the behavior of the ETM cannot be relied upon. Such conditions have not

been validated. When applied to the programming of an event resource, only the output

of that event resource is Unpredictable.

Unpredictable behavior can affect the behavior of the entire system, because the ETM

is capable of causing the core to enter debug state, and external outputs may be used for

other purposes.