User manual

Glossary

Scan chain A scan chain is made up of serially-connected devices that implement boundary scan

technology using a standard JTAG TAP interface. Each device contains at least one TAP

controller containing shift registers that form the chain connected between TDI and

TDO, through which test data is shifted. Processors can contain several shift registers

to enable you to access selected parts of the device.

SCREG The currently selected scan chain number in an ARM TAP controller.

Set See Cache set.

Set-associative cache

In a set-associative cache, lines can only be placed in the cache in locations that

correspond to the modulo division of the memory address by the number of sets. If there

are n ways in a cache, the cache is termed n-way set-associative. The set-associativity

can be any number greater than or equal to 1 and is not restricted to being a power of

two.

Short vector operation

An operation involving more than one destination register and perhaps more than one

source register in the generation of the result for each destination.

Should Be One (SBO)

Should be written as 1 (or all 1s for bit fields) by software. Writing a 0 produces

Unpredictable results.

Should Be Zero (SBZ)

Should be written as 0 (or all 0s for bit fields) by software. Writing a 1 produces

Unpredictable results.

Should Be Zero or Preserved (SBZP)

Should be written as 0 (or all 0s for bit fields) by software, or preserved by writing the

same value back that has been previously read from the same field on the same

processor.

SPICE Simulation Program with Integrated Circuit Emphasis. An accurate transistor-level

electronic circuit simulation tool that can be used to predict how an equivalent real

circuit will behave for given circuit conditions.

SPSR See Saved Program Status Register

Tag The upper portion of a block address used to identify a cache line within a cache. The

block address from the CPU is compared with each tag in a set in parallel to determine

if the corresponding line is in the cache. If it is, it is said to be a cache hit and the line

can be fetched from cache. If the block address does not correspond to any of the tags,

it is said to be a cache miss and the line must be fetched from the next level of memory.

See also Cache terminology diagram on the last page of this glossary.