User manual

Glossary

Modified Virtual Address (MVA)

A Virtual Address produced by the ARM processor can be changed by the current

Process ID to provide a Modified Virtual Address (MVA) for the MMUs and caches.

See also Halt mode.

MPU See Memory Protection Unit.

Multi-ICE A JTAG-based tool for debugging embedded systems.

MVA See Modified Virtual Address.

NCB See Noncachable Buffered.

NCNB See Noncachable Nonbufferable.

Noncachable

Buffered

Is a memory region where reads are performed from main memory and are not allocated

to the cache. Writes are performed to main memory through a write buffer, so processor

core execution can continue while the write is completed to main memory.

Noncachable

Nonbufferable

Is a memory region where reads are performed from main memory and are not allocated

to the cache. Writes are performed to main memory without buffering, so processor core

execution is halted while the write is completed.

PA See Physical Address.

Penalty The number of cycles in which no useful Execute stage pipeline activity can occur

because an instruction flow is different from that assumed or predicted.

Power-on reset See Cold reset.

Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the

pipeline before the preceding instructions have finished executing. Prefetching an

instruction does not mean that the instruction has to be executed.

Prefetch Abort An indication from a memory system to a core that it must halt execution of an

attempted illegal memory access. A Prefetch Abort can be caused by the external or

internal memory system as a result of attempting to access invalid instruction memory.

See also Data Abort, External Abort and Abort.