User manual

Glossary

Little-endian memory

Memory in which:

- a byte or halfword at a word-aligned address is the least significant byte or halfword

within the word at that address

- a byte at a halfword-aligned address is the least significant byte within the halfword at

that address.

See also Big-endian memory.

Load/store architecture

A processor architecture where data-processing operations only operate on register

contents, not directly on memory contents.

Load Store Unit (LSU)

The part of a processor that handles load and store transfers.

LSU See Load Store Unit.

Macrocell A complex logic block with a defined interface and behavior. A typical VLSI system

comprises several macrocells (such as a processor, an ETM, and a memory block) plus

application-specific logic.

Memory bank One of two or more parallel divisions of interleaved memory, usually one word wide,

that enable reads and writes of multiple words at a time, rather than single words. All

memory banks are addressed simultaneously and a bank enable or chip select signal

determines which of the banks is accessed for each transfer. Accesses to sequential

word addresses cause accesses to sequential banks. This enables the delays associated

with accessing a bank to occur during the access to its adjacent bank, speeding up

memory transfers.

Memory coherency A memory is coherent if the value read by a data read or instruction fetch is the value

that was most recently written to that location. Memory coherency is made difficult

when there are multiple possible physical locations that are involved, such as a system

that has main memory, a write buffer and a cache.

Memory Management Unit (MMU)

Hardware that controls caches and access permissions to blocks of memory, and

translates virtual addresses to physical addresses.

Memory Protection Unit (MPU)

Hardware that controls access permissions to blocks of memory. Unlike an MMU, an

MPU does not translate virtual addresses to physical addresses.

Microprocessor See Processor.

Miss See Cache miss.

MMU See Memory Management Unit.