User manual

Glossary
Glossary-6 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Clean A cache line that has not been modified while it is in the cache is said to be clean. To
clean a cache is to write dirty cache entries into main memory. If a cache line is clean,
it is not written on a cache miss because the next level of memory contains the same
data as the cache.
See also Dirty.
Clock gating Gating a clock signal for a macrocell with a control signal and using the modified clock
that results to control the operating state of the macrocell.
Clocks Per
Instruction
See Cycles Per Instuction.
Coherency See Memory coherency.
Cold reset Also known as power-on reset. Starting the processor by turning power on. Turning
power off and then back on again clears main memory and many internal settings. Some
program failures can lock up the processor and require a cold reset to enable the system
to be used again. In other cases, only a warm reset is required.
See also Warm reset.
Communications channel
The hardware used for communicating between the software running on the processor,
and an external host, using the debug interface. When this communication is for debug
purposes, it is called the Debug Comms Channel. In an ARMv6 compliant core, the
communications channel includes the Data Transfer Register, some bits of the Data
Status and Control Register, and the external debug interface controller, such as the
DBGTAP controller in the case of the JTAG interface.
Condensed Reference Format (CRF)
An ARM proprietary file format for specifying test vectors.
Condition field A 4-bit field in an instruction that is used to specify a condition under which the
instruction can execute.
Conditional execution
If the condition code flags indicate that the corresponding condition is true when the
instruction starts executing, it executes normally. Otherwise, the instruction does
nothing.
Content Addressable Memory (CAM)
Memory that is identified by its contents. Content Addressable Memory is used in
CAM-RAM architecture caches to store the tags for cache entries. addressable
memory.