User manual

Glossary
Glossary-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Big-endian memory Memory in which:
- a byte or halfword at a word-aligned address is the most significant byte or halfword
within the word at that address
- a byte at a halfword-aligned address is the most significant byte within the halfword
at that address.
See also Little-endian memory.
Block address An address that comprises a tag, an index, and a word field. The tag bits identify the way
that contains the matching cache entry for a cache hit. The index bits identify the set
being addressed. The word field contains the word address that can be used to identify
specific words, halfwords, or bytes within the cache entry.
See also Cache terminology diagram on the last page of this glossary.
Boundary scan chain
A boundary scan chain is made up of serially-connected devices that implement
boundary scan technology using a standard JTAG TAP interface. Each device contains
at least one TAP controller containing shift registers that form the chain connected
between TDI and TDO, through which test data is shifted. Processors can contain
several shift registers to enable you to access selected parts of the device.
Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which
program execution is to be halted. Breakpoints are inserted by the programmer to enable
inspection of register contents, memory locations, variable values at fixed points in the
program execution to test that the program is operating correctly. Breakpoints are
removed after the program is successfully tested.
See also Watchpoint.
Burst A group of transfers to consecutive addresses. Because the addresses are consecutive,
there is no requirement to supply an address for any of the transfers after the first one.
This increases the speed at which the group of transfers can occur. Bursts over AHB
buses are controlled using the HBURST signals to specify if transfers are single,
four-beat, eight-beat, or 16-beat bursts, and to specify how the addresses are
incremented.
See also Beat.
Bus Interface Unit The Bus Interface Unit (BIU) controls all data accesses across the AHB. It arbitrates and
schedules AHB requests.
Byte An 8-bit data item.