Datasheet

11096AS–ATARM–4-Oct-11

SAM9N12

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of

different event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization

signal

9.27 LCD Controller (LCDC)

• One AHB Master Interface

• Supports Single Scan Active TFT Display

• Supports 12-, 16-, 18- and 24-bit Output Mode through the Spatial Dithering Unit

• Asynchronous Output Mode Supported

• 1, 2, 4, 8 bits per pixel (palletized)

• 12, 16, 18, 19, 24, 25 and 32 bits per pixel (non-palletized)

• Supports One Base Layer (background)

• Little Endian Memory Organization

• Programmable Timing Engine, with Integer Clock Divider

• Programmable Polarity for Data, Line Synchro and Frame Synchro

• Display Size up to 800 x 600

• Color Lookup Table with up to 256 entries

• Programmable Negative and Positive Row Striding

• DMA User interface uses Linked List Structure and Add-to-queue Structure

9.28 True Random Number Generator (TRNG)

• Passed NIST Special Publication 800-22 Tests Suite

• Passed Diehard Random Tests Suite

• Provides a 32-bit Random Number Every 84 Clock Cycles

• 50 Mbits/s throughput for 133 MHz Clock Frequency