Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller BGA 217 (15x15) 16/32-Bit 400 MHz I/O number 105

Features

• Core

– ARM926EJ-S™ ARM

Thumb

Processor running up to 400 MHz @ 1.0V +/- 10%

– 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit

• Memories

– One 128-Kbyte internal ROM embedding bootstrap routine

– One 32-Kbyte internal SRAM, single-cycle access at system speed

– 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static

Memories

– MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error

Correcting Code (PMECC)

• System running up to 133 MHz

– Power-on Reset, Reset Controller, Shut Down Controller, Periodic Interval Timer,

Watchdog Timer and Real Time Clock

– Boot Mode Select Option, Remap Command

– Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators

– Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the

system and one PLL optimized for USB

–Six 32-bit-layer AHB Bus Matrix

– Dual Peripheral Bridge with dedicated programmable clock

– One dual port 8-channel DMA Controller

– Advanced Interrupt Controller and Debug Unit

– Two Programmable External Clock Signals

• Low Power Mode

– Shut Down Controller with four 32-bit battery backup registers

– Clock Generator and Power Management Controller

– Very Slow Clock Operating Mode, Software Programmable Power Optimization

Capabilities

• Peripherals

– LCD Controller

– USB Device Full Speed with dedicated On-Chip Transceiver

– USB Host Full Speed with dedicated On-Chip Transceiver

– One High speed SD card and SDIO Host Controller

– Two Master/Slave Serial Peripheral Interfaces

– Two Three-channel 32-bit Timer/Counters

– One Synchronous Serial Controller

– One Four-channel 16-bit PWM Controller

– Two Two-wire Interfaces

– Four USARTs plus two UARTs

– One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive

Touch screen support

• Customizing

– TRNG True Random Number Generator compliant with NIST Special Publication

800-22

– 320 Fuse bits for device configuration, including JTAG disable and forced boot

from the on-chip ROM

• I/O

– Four 32-bit Parallel Input/Output Controllers

– 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os

– Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input

– Individually Programmable Open-drain, Pull-up and Pull-down Resistor,

Synchronous Output

– Package: 217-ball BGA, pitch 0.8 mm

AT91SAM

ARM-based

Embedded MPU

SAM9N12

Summary

11096AS–ATARM–4-Oct-11

Summary of content (42 pages)

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Features • Core • • • • • • – ARM926EJ-S™ ARM® Thumb® Processor running up to 400 MHz @ 1.
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1. Description The ARM926EJ-S based SAM9N12 features the frequently requested combination of user interface functionality and high data rate connectivity, including LCD Controller, resistive touchscreen, multiple UARTs, SPI, I2C, full speed USB Host and Device and SDIO. The SAM9N12 supports the latest generation of LPDDR/DDR2 and NAND Flash memory interfaces for program and data storage.
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SAM9N12 2.
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3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1.
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SAM9N12 Table 3-1.
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Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Universal Asynchronous Receiver Transmitter - UARTx UTXDx UARTx Transmit Data Output URXDx UARTx Receive Data Input Synchronous Serial Controller - SSC TD SSC Transmit Data Output RD SSC Receive Data Input TK SSC Transmit Clock I/O RK SSC Receive Clock I/O TF SSC Transmit Frame Sync I/O RF SSC Receive Frame Sync I/O Timer Counter - TCx x=0..
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SAM9N12 Table 3-1. Signal Description List (Continued) Signal Name Function Type LCDDEN LCD Data Enable Output LCDPWM LCD Contrast Control Output LCDDISP LCD Display Enable Output Active Level Analog-to-Digital Converter - ADC Table 3-2.
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4. Package and Pinout The SAM9N12 is available in 217-ball BGA. 4.1 Mechanical Overview of the 217-ball BGA Package Figure 4-1 shows the orientation of the 217-ball BGA Package. Figure 4-1. Orientation of the 217-ball BGA Package TOP VIEW 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U BALL A1 4.2 217-ball BGA Package Pinout Table 4-1.
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SAM9N12 Table 4-1.
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Table 4-1.
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SAM9N12 Table 4-1.
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Table 4-1.
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SAM9N12 Table 4-1.
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Table 4-1.
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SAM9N12 5. Power Considerations 5.1 Power Supplies The SAM9N12 has several types of power supply pins: Table 5-1. Name Voltage Range, nominal Associated Ground VDDCORE 0.9-1.1V, 1.0V GNDCORE the core, including the processor, the embedded memories and the peripherals, the internal 12 MHz RC GNDIOM the External Memory Interface I/O lines GNDIOM the NAND Flash I/O and control, D16-D32 and multiplexed SMC lines VDDIOM VDDNF 5.2 5.2.1 SAM9N12 Power Supplies 1.65-1.95V, 1.8V 3.0-3.6V, 3.3V 1.
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DDR2 or LPDDR or 16-bit LPSDR (1.8V) D[15:0] D[15:0] NAND Flash (1.8V) D[15:0] A[22:21] ALE CLE EBI 32bit SDRAM (3.3V) D[15:0] D[31:16] D[15:0] D[31:16] NAND Flash (3.3V) D[15:0] A[22:21] ALE CLE EBI In the following example the NAND Flash and the external RAM (DDR2 or LPDDR or 16bit LPSDR) are NOT in the same power supply range (NFD0_ON_D16 = 1). DDR2 or LPDDR or 16-bit LPSDR (1.8V) D[15:0] D[15:0] NAND Flash (3.
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SAM9N12 6. Memories Figure 6-1.
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6.1 Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5.
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SAM9N12 6.3 External Memories Overview The SAM9N12 features a External Bus Interface to offer interface to a wide range of external memories and to any parallel peripheral. 6.3.
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– Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices) • Energy-saving Capabilities – Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported • SDRAM Power-up Initialization by Software • CAS Latency of 2, 3 Supported • Reset Function Supported (DDR2-SDRAM) • ODT (On-die Termination) Not Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported • DDR2-SDRAM with Eight Internal Banks Supported • Linear and interle
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SAM9N12 7. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories. 7.
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7.2 System Controller Block DIagram Figure 7-1. SAM9N12 System Controller Block Diagram System Controller VDDCORE Powered irq fiq periph_irq[2..
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SAM9N12 7.3 Chip Identification • Chip ID: 0x819A_05A1 • SAM9N12 Chip ID Extension: 6 • JTAG ID: 0x05B3_003F • ARM926 TAP ID: 0x0792_603F 7.4 Backup Section The SAM9N12 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • Real Time Counter (RTC) • Shutdown Controller • 4 backup registers • Slow Clock Control Register (SCKCR) • A part of the reset Controller (RSTC) • This section is powered by the VDDBU rail. 7.
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8. Peripherals 8.1 Peripheral Mapping As shown in Figure 6-1, the Peripherals are mapped in the upper 256M bytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. 8.2 Peripheral Identifiers Table 8-1 defines the Peripheral Identifiers of the SAM9N12.
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SAM9N12 Table 8-1. SAM9N12 Peripheral Identifiers (Continued) Instance ID Instance name 27 Reserved 28 SSC 29 Reserved 30 TRNG True Random Number Generator 31 AIC Advanced Interrupt Controller 8.3 8.3.
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• ‘I’/’O’ Indicates whether the signal is input or output state. • “PU”/”PD” Indicates whether Pull-up or Pull-down, or nothing is enabled. • “ST” Indicates if Schmitt Trigger is enabled. Note: Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address line 20 with Pull-Down. 8.4.
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SAM9N12 9. Embedded Peripherals 9.1 Advanced Interrupt Controller (AIC) • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, PMECC, etc.
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9.3 Real-time Clock (RTC) • Low power consumption • Full asynchronous design • Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 9.4 Periodic Interval Timer (PIT) • 20-bit Programmable Counter plus 12-bit Interval Counter • Reset-on-read Feature • Both Counters Work on Master Clock/16 • AMBA-compliant Interface – Interfaces to the ARM® Advanced Peripheral Bus 9.
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SAM9N12 PMC output clocks: • Processor Clock PCK. • Master Clock MCK, in particular to the Matrix, the memory interfaces, the peripheral bridge. The divider can be 2, 3 or 4. • Each peripheral embeds its own divider, programmable in the PMC User Interface. • 250MHz DDR system clock Note: DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK). • LCD pixel clock that can use DDR system clock or MCK, the choice is done in the LCD user interface.
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9.
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SAM9N12 9.12 Programmable Multibit ECC Error Location Controller (PMERRLOC) • Provides Hardware Acceleration for determining roots of polynomials defined over a finite field • Programmable Finite Field GF(2^13) or GF(2^14) • Finds Roots of Error Locator Polynomial • Programmable Number of Roots 9.
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– Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported • SDRAM Power-up Initialization by Software • CAS Latency of 2, 3 Supported • Reset Function Supported (DDR2-SDRAM) • ODT (On-die Termination) Not Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported • DDR2-SDRAM with Eight Internal Banks Not Supported • Clock Frequency Change in Precharge Power-down Mode Not Supported • OCD (Off-chip Driver) Mode Not Supported 9.
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SAM9N12 – Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple transaction completion or Error condition 9.16 USB Device Full Speed (UDP) • USB V2.0 full-speed compliant, 12 MBits per second • Embedded USB V2.
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• Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device 9.
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SAM9N12 9.22 Two Wire Interface (TWI) • Two TWIs • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations • Supports either master or slave modes • Compatible with Standard Two-wire Serial Memories • Master, Multi-master and Slave Mode Operation • Bit Rate: Up to 400 Kbits • General Call Supported in Slave mode 9.
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– Automatic processing and verification of the “Synch Break” and the “Synch Field” – The “Synch Break” is detected even if it is partially superimposed with a data byte – Automatic Identifier parity calculation/sending and verification – Parity sending and verification can be disabled – Automatic Checksum calculation/sending and verification – Checksum sending and verification can be disabled – Support both “Classic” and “Enhanced” checksum types – Full LIN error checking and reporting – Frame Slot Mode: th
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SAM9N12 • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 9.
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10. Mechanical Characteristics 10.1 217-ball BGA Package Figure 10-1.
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SAM9N12 10.2 Marking All devices are marked with the Atmel logo and the ordering code.
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11. AT91SAM9N12 Ordering Information Table 11-1.
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SAM9N12 Revision History In the tables that follow, the most recent version appears first. “rfo” denotes expert input during the update process. Doc. Rev Comments 11096AS First issue Change Request Ref.
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg.