Datasheet

32
11096AS–ATARM–4-Oct-11
SAM9N12
– Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported
• SDRAM Power-up Initialization by Software
• CAS Latency of 2, 3 Supported
• Reset Function Supported (DDR2-SDRAM)
• ODT (On-die Termination) Not Supported
• Auto Precharge Command Not Used
• SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
• DDR2-SDRAM with Eight Internal Banks Not Supported
• Clock Frequency Change in Precharge Power-down Mode Not Supported
• OCD (Off-chip Driver) Mode Not Supported
9.15 AHB DMA Controller (DMAC)
• DMAC is full featured and optimized for memory-to-memory transfers
• Acting as Two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
– Source / destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
lists
– Scatter support for placing fields into a system memory area from a contiguous
transfer. Writing a stream of data into non-contiguous fields in system memory
– Gather support for extracting fields from a system memory area into a contiguous
transfer
– User enabled auto-reloading of source, destination and control registers from initially
programmed values at the end of a block transfer
– Auto-loading of source, destination and control registers from system memory at end
of block transfer in block chaining mode
– Unaligned system address to data transfer width supported in hardware
– Picture-In-Picture Mode
• Channel Buffering
– 16-word FIFO
– Automatic packing/unpacking of data to fit FIFO width
• Channel Control
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
– Suspend DMA operation
– Programmable DMA lock transfer support
• Transfer Initiation
– Support for Software handshaking interface. Memory mapped registers can be used
to control the flow of a DMA transfer in place of a hardware handshaking interface
• Interrupt