Datasheet

31
11096AS–ATARM–4-Oct-11
SAM9N12
9.12 Programmable Multibit ECC Error Location Controller (PMERRLOC)
• Provides Hardware Acceleration for determining roots of polynomials defined over a finite
field
• Programmable Finite Field GF(2^13) or GF(2^14)
• Finds Roots of Error Locator Polynomial
• Programmable Number of Roots
9.13 AHB Static Memory Controller (AHB SMC)
• 6 Chip Selects Available
• 64-Mbyte Address Space per Chip Select
• 8-, 16- or 32-bit Data Bus
• Word, Halfword, Byte Transfers
• Byte Write or Byte Select Lines
• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
• Programmable Data Float Time per Chip Select
• Compliant with LCD Module
• External Wait Request
• Automatic Switch to Slow Clock Mode
• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
9.14 AHB DDR/SDR SDRAM Controller (DDRSDRC)
• AMBA Compliant Interface, interfaces Directly to the ARM® Advanced High performance Bus
(AHB)
– Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth
and Minimizes Transaction Latency
– AHB Transfer: Word, Half Word, Byte Access
• Supports DDR2-SDRAM, Low-power DDR-SDRAM, SDR-SDRAM and Low-power
SDRSDRAM
• Numerous Configurations Supported
– 2K, 4K, 8K, 16K Row Address Memory Parts
– SDRAM with Four Internal Banks
– SDR-SDRAM with 16- or 32-bit Data Path
– DDR-SDRAM with 16-bit Data Path
– One Chip Select for SDRAM Device (256 Mbyte Address Space)
• Programming Facilities
– Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces
Average Latency of Transactions)
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
– Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices)
• Energy-saving Capabilities