Datasheet

30
11096AS–ATARM–4-Oct-11
SAM9N12
9.10 Debug Unit (DBGU)
• System Peripheral to Facilitate Debug of Atmel
®
ARM
®
-based Systems
• Composed of Four Functions
–Two-pin UART
– Debug Communication Channel (DCC) Support
– Chip ID Registers
– ICE Access Prevention
•Two-pin UART
– Implemented Features are USART Compatible
– Independent Receiver and Transmitter with a Common Programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Interrupt Generation
– Support for Two DMA Channels with Connection to Receiver and Transmitter
• Debug Communication Channel Support
– Offers Visibility of COMMRX and COMMTX Signals from the ARM Processor
– Interrupt Generation
• Chip ID Registers
– Identification of the Device Revision, Sizes of the Embedded Memories, Set of
Peripherals
• ICE Access Prevention
– Enables Software to Prevent System Access Through the ARM Processor’s ICE
– Prevention is Made by Asserting the NTRST Line of the ARM Processor’s ICE
9.11 Programmable Multibit ECC Controller (PMECC)
• Multibit Error Correcting Code.
• Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes.
• Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 bit of errors per sector.
• Programmable Sector Size: 512 bytes or 1024 bytes.
• Programmable Number of Sectors per page: 1, 2, 4 or 8 sectors of data per page.
• Programmable Spare Area Size.
• Supports Spare Area ECC Protection.
• Supports 8 kbytes page size using 1024 bytes per sector and 4 kbytes page size using
512 bytes per sector.
• Configurable through APB interface
• Multibit Error Detection is Interrupt Driven