Datasheet

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11096AS–ATARM–4-Oct-11
SAM9N12
PMC output clocks:
• Processor Clock PCK.
• Master Clock MCK, in particular to the Matrix, the memory interfaces, the peripheral bridge.
The divider can be 2, 3 or 4.
• Each peripheral embeds its own divider, programmable in the PMC User Interface.
• 250MHz DDR system clock
Note: DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
• LCD pixel clock that can use DDR system clock or MCK, the choice is done in the LCD user
interface.
• USB clocks (USB48M and USB12M) thanks to PLLBCK.
• Two programmable clock outputs: PCK0 and PCK1
This allows the software control of five flexible operating modes:
• Normal Mode, processor and peripherals running at a programmable frequency
• Idle Mode, processor stopped waiting for an interrupt
• Slow Clock Mode, processor and peripherals running at low frequency
• Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor
stopped waiting for an interrupt
• Backup Mode, Main Power Supplies off, VDDBU powered by a battery
9.9 PIO Controllers (PIO)
• Up to 32 Programmable I/O Lines
• Fully Programmable through Set/Clear Registers
• Multiplexing of Four Peripheral Functions per I/O Line
• For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
– Input Change Interrupt
– Programmable Glitch Filter
– Programmable Debouncing Filter
– Multi-drive Option Enables Driving in Open Drain
– Programmable Pull Up on Each I/O Line
– Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
– Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge,
Low Level or High Level
– Lock of the Configuration by the Connected Peripheral
• Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write
• Write Protect Registers
• Programmable I/O Delay
• Programmable Schmitt Trigger Inputs