Datasheet

27
11096AS–ATARM–4-Oct-11
SAM9N12
9. Embedded Peripherals
9.1 Advanced Interrupt Controller (AIC)
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, PMECC, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• One External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
•Protect Mode
– Easy debugging by preventing automatic operations when protect models are
enabled
•Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.2 Reset Controller (RSTC)
• Manages All Resets of the System, Including
– External Devices Through the NRST Pin
– Processor Reset
– Peripheral Set Reset
• Based on 2 Embedded Power-on Reset Cells
• Reset Source Status
– Status of the Last Reset
– Either Power-up Reset, Software Reset, User Reset, Watchdog Reset
• External Reset Signal Shaping
•AMBA
®
-compliant Interface
– Interfaces to the ARM® Advanced Peripheral Bus