Datasheet

11096AS–ATARM–4-Oct-11

SAM9N12

• ‘I’/’O’

Indicates whether the signal is input or output state.

• “PU”/”PD”

Indicates whether Pull-up or Pull-down, or nothing is enabled.

•“ST”

Indicates if Schmitt Trigger is enabled.

Note: Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is

configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”.

That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address

line 20 with Pull-Down.

8.4.2 PIO Line Selection

Peripheral A, B or C is selected thanks to the PIO_ABCDSR1 and PIO_ABCDSR2 registers in

the PIO Controller Interface.

8.5 Fuse Box Features

SAM9N12 embeds 320 One Time Programming (OTP) bits. When the OTP bit is set, it is seen

as ‘1’. The user interface allows the user to perform the following operations:

8.5.1 Read

• 10 registers SR0-SR9 that reflect OTP bit state

• MSK field (write-once) allow user to mask registers SR1 to SR9

• All OTP bits are read as ‘1’ when VDDFUSE is floating, all security features are set.

8.5.2 Write

• Done in one 32-bit DATA register

• SEL field to select the 32-bit word 0 to 9

Table 8-2. PIO Line Selection

Px value in PIO_ABCDSR2 Px value in PIO_ABCDSR1 A, B or C

00A

01B

10C

Table 8-3. Special OTP Bit Description

Bit Number Bit Name Function

OTP bit writing is disabled if set

OTP bits are not accessible in test mode

BMS sampling is disabled if set, system boots systematically out of the

ROM code

2 J JTAG is disabled if set

3-7 3-7 Reserved