Datasheet

23
11096AS–ATARM–4-Oct-11
SAM9N12
7.3 Chip Identification
• Chip ID: 0x819A_05A1
• SAM9N12 Chip ID Extension: 6
• JTAG ID: 0x05B3_003F
• ARM926 TAP ID: 0x0792_603F
7.4 Backup Section
The SAM9N12 features a Backup Section that embeds:
• RC Oscillator
• Slow Clock Oscillator
• Real Time Counter (RTC)
• Shutdown Controller
• 4 backup registers
• Slow Clock Control Register (SCKCR)
• A part of the reset Controller (RSTC)
• This section is powered by the VDDBU rail.
7.5 Security Features
The SAM9N12 features:
• 320 OTP bits array
• Secure bootloader selectable by a dedicated fuse bit
• Bits in SFR register to forbid ROM and OTP read access
The OTP array enables the user to set security features and program device configuration
The secure bootloader allows:
• Keeping the firmware stored in Non-Volatile memory encrypted
• Decryption, in internal SRAM only, the firmware using the customer’s crypto key burned in
the fuse bits
• The encryption/decryption uses high strength hardware, AES256