Datasheet

11096AS–ATARM–4-Oct-11

SAM9N12

– Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices)

• Energy-saving Capabilities

– Self-refresh, Power-down, Active Power-down and Deep Power-down Modes

Supported

• SDRAM Power-up Initialization by Software

• CAS Latency of 2, 3 Supported

• Reset Function Supported (DDR2-SDRAM)

• ODT (On-die Termination) Not Supported

• Auto Precharge Command Not Used

• SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported

• DDR2-SDRAM with Eight Internal Banks Supported

• Linear and interleaved decoding supported

• Clock Frequency Change in Precharge Power-down Mode Not Supported

• OCD (Off-chip Driver) Mode Not Supported

6.3.4 Programmable Multi-bit Error Correcting Code (PMECC)

• Multibit Error Correcting Code.

• Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes.

• Programmable Error Correcting Capability: 2, 4, 8, 16 and 24 bit of errors per block.

• Programmable block size: 512 bytes or 1024 bytes.

• Programmable number of block per page: 1, 2, 4 or 8 blocks of data per page.

• Programmable spare area size.

• Supports spare area ECC protection.

• Supports 8 kbytes page size using 1024 bytes/block and 4 kbytes page size using 512

bytes/block.

• Multibit Error detection is interrupt driven.

6.3.5 Programmable Multi-bit ECC Error Location (PMERRLOC)

• Provides hardware acceleration for determining roots of polynomials defined over a finite field

• Programmable finite Field GF(2^13) or GF(2^14)

• Finds roots of error-locator polynomial.

• Programmable number of roots.