Datasheet

2
11096AS–ATARM–4-Oct-11
SAM9N12
1. Description
The ARM926EJ-S based SAM9N12 features the frequently requested combination of user inter-
face functionality and high data rate connectivity, including LCD Controller, resistive touch-
screen, multiple UARTs, SPI, I2C, full speed USB Host and Device and SDIO.
The SAM9N12 supports the latest generation of LPDDR/DDR2 and NAND Flash memory inter-
faces for program and data storage. An internal 125 MHz multi-layer bus architecture associated
with 8 DMA channels, a distributed memory including a 32-Kbyte SRAM, sustains the high band-
width required by the processor and the high speed peripherals.
The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory
interface and peripheral I/Os. This feature completely eliminates the need for any external level
shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing.
The SAM9N12 power management controller features efficient clock gating and a battery
backup section minimizing power consumption in active and standby modes.