Datasheet

SAM9M10 [SUMMARY]

6355ES–ATARM–12-Mar-13

z Vertical and horizontal resolutions up to 2048 x 2048

z Preview Path up to 640*480

z Support for packed data formatting for YCbCr 4:2:2 formats

z Preview scaler to generate smaller size image

10.15 8-channel DMA (DMA)

z Acting as two Matrix Masters

z Embeds 8 unidirectional channels with programmable priority

z Address Generation

z Source/Destination address programming

z Address increment, decrement or no change

z DMA chaining support for multiple non-contiguous data blocks through use of linked lists

z Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of

data into non-contiguous fields in system memory

z Gather support for extracting fields from a system memory area into a contiguous transfer

z User enabled auto-reloading of source, destination and control registers from initially programmed values at

the end of a block transfer

z Auto-loading of source, destination and control registers from system memory at end of block transfer in

block chaining mode

z Unaligned system address to data transfer width supported in hardware

z Channel Buffering

z 16-word FIFO

z Automatic packing/unpacking of data to fit FIFO width

z Channel Control

z Programmable multiple transaction size for each channel

z Support for cleanly disabling a channel without data loss

z Suspend DMA operation

z Programmable DMA lock transfer support

z Transfer Initiation

z Support for Software handshaking interface. Memory mapped registers can be used to control the flow of a

DMA transfer in place of a hardware handshaking interface

z Interrupt

z Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple

transaction completion or Error condition

10.16 True Random Number Generator (TRNG)

z Passed NIST Special Publication 800-22 Tests Suite

z Passed Diehard Random Tests Suite

z Provides a 32-bit Random Number Every 84 Clock Cycles

z For 133 MHz Clock Frequency, Throughput Close to 50 Mbits/s

10.17 Video Decoder (VDEC)

z Little-endian and Big-endian support.

Decoder supported standards:

z MPEG-4 Simple and Advanced Profile, levels 0-5

z H.264 Baseline Profile, levels 1-3.1