Datasheet

SAM9M10 [SUMMARY]

6355ES–ATARM–12-Mar-13

6. Processor and Architecture

6.1 ARM926EJ-S Processor

z RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration

z Two Instruction Sets

z ARM High-performance 32-bit Instruction Set

z Thumb High Code Density 16-bit Instruction Set

z DSP Instruction Extensions

z 5-Stage Pipeline Architecture:

z Instruction Fetch (F)

z Instruction Decode (D)

z Execute (E)

z Data Memory (M)

z Register Write (W)

z 32-KByte Data Cache, 32-KByte Instruction Cache

z Virtually-addressed 4-way Associative Cache

z Eight words per line

z Write-through and Write-back Operation

z Pseudo-random or Round-robin Replacement

z Write Buffer

z Main Write Buffer with 16-word Data Buffer and 4-address Buffer

z DCache Write-back Buffer with 8-word Entries and a Single Address Entry

z Software Control Drain

z Standard ARM v4 and v5 Memory Management Unit (MMU)

z Access Permission for Sections

z Access Permission for large pages and small pages can be specified separately for each quarter of the

page

z 16 embedded domains

z Bus Interface Unit (BIU)

z Arbitrates and Schedules AHB Requests

z Separate Masters for both instruction and data access providing complete Matrix system flexibility

z Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface

z On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)

z TCM Interface