Datasheet

997
SAM9M10 [DATASHEET]
6355FATARM12-Mar-13
42.7.9 PWM Channel Mode Register
Name: PWM_CMR[0..3]
Addresses: 0xFFFB8200 [0], 0xFFFB8220 [1], 0xFFFB8240 [2], 0xFFFB8260 [3]
Access: Read/Write
CPRE: Channel Pre-scaler
CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
CPD: Channel Update Period
0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––CPDCPOL CALG
76543210
–––– CPRE
CPRE Channel Pre-scaler
0000MCK
0001MCK/2
0010MCK/4
0011MCK/8
0 1 0 0 MCK/16
0 1 0 1 MCK/32
0 1 1 0 MCK/64
0 1 1 1 MCK/128
1 0 0 0 MCK/256
1 0 0 1 MCK/512
1 0 1 0 MCK/1024
1011CLKA
1100CLKB
Other Reserved