Datasheet

990
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
42.6.3.4 Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the correspond-
ing channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is dis-
abled by setting the corresponding bit in the PWM_IDR register.