Datasheet
971
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
41.6.13 DMAC Channel x [x = 0..7] Source Address Register
Name: DMAC_SADDRx [x = 0..7]
Addresses: 0xFFFFEC3C [0], 0xFFFFEC64 [1], 0xFFFFEC8C [2], 0xFFFFECB4 [3], 0xFFFFECDC [4],
0xFFFFED04 [5], 0xFFFFED2C [6], 0xFFFFED54 [7]
Access: Read-write
Reset: 0x00000000
• SADDRx
Channel x source address. This register must be aligned with the source transfer width.
41.6.14 DMAC Channel x [x = 0..7] Destination Address Register
Name: DMAC_DADDRx [x = 0..7]
Addresses: 0xFFFFEC40 [0], 0xFFFFEC68 [1], 0xFFFFEC90 [2], 0xFFFFECB8 [3], 0xFFFFECE0 [4], 0xFFFFED08 [5],
0xFFFFED30 [6], 0xFFFFED58 [7]
Access: Read-write
Reset: 0x00000000
• DADDRx
Channel x destination address. This register must be aligned with the destination transfer width.
31 30 29 28 27 26 25 24
SADDRx
23 22 21 20 19 18 17 16
SADDRx
15 14 13 12 11 10 9 8
SADDRx
76543210
SADDRx
31 30 29 28 27 26 25 24
DADDRx
23 22 21 20 19 18 17 16
DADDRx
15 14 13 12 11 10 9 8
DADDRx
76543210
DADDRx