Datasheet

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

– DMA chaining support for multiple non-contiguous data blocks through use of linked lists

– Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a

stream of data into non-contiguous fields in system memory

– Gather support for extracting fields from a system memory area into a contiguous transfer

– User enabled auto-reloading of source, destination and control registers from initially programmed

values at the end of a block transfer

– Auto-loading of source, destination and control registers from system memory at end of block transfer

in block chaining mode

– Unaligned system address to data transfer width supported in hardware

• Channel Buffering

– 16-word FIFO

– Automatic packing/unpacking of data to fit FIFO width

• Channel Control

– Programmable multiple transaction size for each channel

– Support for cleanly disabling a channel without data loss

– Suspend DMA operation

– Programmable DMA lock transfer support

• Transfer Initiation

– Support for Software handshaking interface. Memory mapped registers can be used to control the flow

of a DMA transfer in place of a hardware handshaking interface

• Interrupt

– Programmable Interrupt generation on DMA Transfer completion Block Transfer completion,

Single/Multiple transaction completion or Error condition