Datasheet

904
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
40.9 Conversion Triggers
Conversions of the active analog channels are started with a software or a hardware trigger.
The software trigger is provided by writing the “TSADCC Control Register” with the bit START at 1.
The hardware trigger can be selected by the filed TRGMOD in the TSADCC Trigger Register (TSADCC_TRGR)
between:
• an edge, either rising or falling or any, detected on the external trigger pin TSADTRG
• the Pen Detect, depending on how the PENDET bit is set in the “TSADCC Mode Register”
• a continuous trigger, meaning the TSADCC restarts the next sequence as soon as it finishes the current one, in
this case, only one software trigger is required at the beginning
• a periodic trigger, which is defined by programming the field TRGPER in the “TSADCC Trigger Register”
Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is
selected, the start of a conversion can still be initiated by the software trigger.
40.10 Operating Modes
The Touch Screen ADC Controller features several operating modes, each defining a conversion sequence:
• The ADC Mode: at each trigger, all the enabled channels are converted
• The Touch Screen Mode: at each trigger, the touch screen inputs are converted with the switches accordingly
set and the results are processed and stored in the corresponding data registers
• The Interleaved Mode: at each trigger, the 8 conversions for the touch screen and the analog inputs conversions
are performed. Only the analog inputs results are managed by the PDC and the touch screen conversions can
be performed less often than the analog inputs.
The Operating Mode of the TSADCC is programmed in the field TSAMOD in the “TSADCC Mode Register”.
The conversion sequences for each Operating Mode are described in the following paragraphs.
The conversion sequencer, combined with the Sleep Modes, allows automatic processing with minimum processor
intervention and optimized power consumption. In any case, the sequence starts with a trigger event.
Note: The reference voltage pins always remain connected in normal mode as in sleep mode.
40.10.1 ADC Mode
In the ADC Mode, the active channels are defined by the “TSADCC Channel Status Register”, which is defined by
writing the “TSADCC Channel Enable Register” and “TSADCC Channel Disable Register”. The results are stored
in the “TSADCC Channel Data Register x (x = 0..7)” and in the “TSADCC Last Converted Data Register”, so that
data transfers by using the PDC are possible.
At each trigger, the following sequence is performed:
3. If SLEEP is set, wake up the ADC cell and wait for the Startup Time.
4. If Channel 0 is enabled, convert Channel 0 and store result in both TSADCC_CDR0 and TSADCC_LCDR.
5. If Channel 1 is enabled, convert Channel 1 and store result in both TSADCC_CDR1 and TSADCC_LCDR.
6. If Channel 2 is enabled, convert Channel 2 and store result in both TSADCC_CDR2 and TSADCC_LCDR.
7. If Channel 3 is enabled, convert Channel 3 and store result in both TSADCC_CDR3 and TSADCC_LCDR.
8. If Channel 4 to Channel 7 are enabled, convert the Channels and store result in the corresponding
TSADCC_CDRx and TSADCC_LCDR.
9. If SLEEP is set, sleep down the ADC cell.
If the PDC is enabled, all the converted data are transferred contiguously in the memory buffer. The bit LOWRES
defines which resolution is used, either 8-bit or 10-bit, and thus the width of the PDC memory buffer.