Datasheet

769
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
36.6.27 EMAC Statistic Registers
These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read
frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit
is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statis-
tics register block contains the following registers.
36.6.27.1 Pause Frames Received Register
Name: EMAC_PFR
Address: 0xFFFBC03C
Access: Read-write
• FROK: Pause Frames received OK
A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit
8 set in network configuration register) and has no FCS, alignment or receive symbol errors.
36.6.27.2 Frames Transmitted OK Register
Name: EMAC_FTO
Address: 0xFFFBC040
Access: Read-write
• FTOK: Frames Transmitted OK
A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
FROK
76543210
FROK
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
FTOK
15 14 13 12 11 10 9 8
FTOK
76543210
FTOK