Datasheet

740
SAM9M10 [DATASHEET]
6355FATARM12-Mar-13
if it matches the hash address function.
if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
if the EMAC is configured to copy all frames.
The register receive buffer queue pointer points to the next entry (see Table 36-1 on page 728) and the EMAC
uses this as the address in system memory to write the frame to. Once the frame has been completely and suc-
cessfully received and written to system memory, the EMAC then updates the receive buffer descriptor entry with
the reason for the address match and marks the area as being owned by software. Once this is complete an inter-
rupt receive complete is set. Software is then responsible for handling the data in the buffer and then releasing the
buffer by writing the ownership bit back to 0.
If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is
set. If there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer
not available is set. If the frame is not successfully received, a statistic register is incremented and the frame is dis-
carded without informing software.