Datasheet

675
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
As soon as the command register is written, then the status bit CMDRDY in the status register (HSMCI_SR) is
cleared.
It is released and the end of the card response.
If the command requires a response, it can be read in the HSMCI response register (HSMCI_RSPR). The
response size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error detec-
tion to prevent any corrupted data during the transfer.
The following flowchart shows how to send a command to the card and read the response if needed. In this exam-
ple, the status register bits are polled but setting the appropriate bits in the interrupt enable register (HSMCI_IER)
allows using an interrupt method.
Figure 35-7. Command/Response Functional Flow Diagram
Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed MultiMe-
dia Card specification).
RETURN OK
RETURN ERROR
(1)
Set the command argument
HSMCI_ARGR = Argument
(1)
Set the command
HSMCI_CMDR = Command
Read HSMCI_SR
CMDRDY
Status error flags
Read response if required
Ye s
Wait for command
ready status flag
Check error bits in the
status register
(1)
0
1