Datasheet

566
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 32-20. TWI Read Operation with Multiple Data Bytes with or without Internal Address
Internal address size = 0
Start the transfer
TWI_CR = START
Stop the transfer
TWI_CR = STOP
Read Status register
RXRDY = 1
Last data to read
but one
Read status register
TXCOMP = 1
END
Set the internal address
TWI_IADR = address
Ye s
Ye s
Ye s
No
Ye s
Read Receive Holding register (TWI_RHR)
No
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
No
Read Status register
RXRDY = 1
Ye s
Read Receive Holding register (TWI_RHR)
No