Datasheet

565

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Figure 32-19. TWI Read Operation with Single Data Byte and Internal Address

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address

- Internal address size (IADRSZ)

- Transfer direction bit

Read ==> bit MREAD = 1

Read Status register

TXCOMP = 1

END

BEGIN

Ye s

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Ye s

Set the internal address

TWI_IADR = address

Start the transfer

TWI_CR = START | STOP

Read Status register

RXRDY = 1

Read Receive Holding register