Datasheet
564
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 32-18. TWI Read Operation with Single Data Byte without Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Transfer direction bit
Read ==> bit MREAD = 1
Start the transfer
TWI_CR = START | STOP
Read status register
RXRDY = 1
Read Status register
TXCOMP = 1
END
BEGIN
Ye s
Ye s
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Read Receive Holding Register
No
No