Datasheet

503
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 31-38. SPI Transfer Format (CPHA=1, 8 bits per transfer)
Figure 31-39. SPI Transfer Format (CPHA=0, 8 bits per transfer)
31.7.7.4 Receiver and Transmitter Control
See “Receiver and Transmitter Control” on page 479.
6
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
MISO
SPI Master ->RXD
SPI Slave -> TXD
SCK
(CPOL = 0)
SCK
(CPOL = 1)
1 2345 7
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
2
2
6