Datasheet

50
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
10.4.2 Test Environment
Figure 10-3 on page 50 shows a test environment example. Test vectors are sent and interpreted by the tester. In
this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be
connected to form a single scan chain.
Figure 10-3. Application Test Environment Example
10.5 Debug and Test Pin Description
JTAG
Interface
Test Adaptor
Chip 2Chip n
Chip 1
ICE/JTAG
Tester
SAM9M10-based Application Board In Test
SAM9M10
Table 10-1. Debug and Test Pin List
Pin Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Mode Select Input High
ICE and JTAG
NTRST Test Reset Signal Input Low
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
RTCK Returned Test Clock Output
JTAGSEL JTAG Selection Input
Debug Unit
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output