Datasheet

446
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 30-6. Input Change Interrupt Timings
30.4.11 Write Protected Registers
To prevent any single software error that may corrupt the PIO behavior, the registers listed below can be write-pro-
tected by setting the WPEN bit in the PIO Write Protect Mode Register (PIO_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the PIO Write Protect Status Reg-
ister (PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the PIO Write Protect Status Register (PIO_WPSR).
List of the write-protected registers:
• “PIO Enable Register” on page 451
• “PIO Disable Register” on page 451
• “PIO Output Enable Register” on page 452
• “PIO Output Disable Register” on page 453
• “PIO Input Filter Enable Register” on page 454
• “PIO Input Filter Disable Register” on page 454
• “PIO Set Output Data Register” on page 455
• “PIO Clear Output Data Register” on page 456
• “PIO Multi-driver Enable Register” on page 459
• “PIO Multi-driver Disable Register” on page 460
• “PIO Pull Up Disable Register” on page 461
• “PIO Pull Up Enable Register” on page 461
• “PIO Peripheral A Select Register” on page 462
• “PIO Peripheral B Select Register” on page 463
• “PIO Output Write Enable Register” on page 464
• “PIO Output Write Disable Register” on page 464
MCK
Pin Level
Read PIO_ISR
APB Access
PIO_ISR
APB Access