Datasheet
370
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 27-8. Status Register Flags Behavior
Figure 27-9 shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer
(ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags behavior within the SPI_SR (Sta-
tus Register) during an 8-bit data transfer in fixed mode with the Peripheral Data Controller involved. The PDC is
programmed to transfer and receive three data. The next pointer and counter are not used. The RDRF and TDRE
are not shown because these flags are managed by the PDC when using the PDC.
Figure 27-9. PDC Status Register Flags Behavior
6
SPCK
MOSI
(from master)
MISO
(from slave)
NPCS0
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
RDRF
TDRE
TXEMPTY
Write in
SPI_TDR
RDR read
shift register empty
MSB LSB654321
SPCK
MOSI
(from master)
NPCS0
MSB LSB654321
12
3
ENDTX
TXEMPTY
MSB LSB654321
MSB LSB654321
MISO
(from slave)
MSB LSB654321
MSB LSB654321
ENDRX
TXBUFE
RXBUFF