Datasheet

37
SAM9M10 [DATASHEET]
6355FATARM12-Mar-13
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual.
Table 9-2 gives the ARM instruction mnemonic list.
Table 9-2. ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
MOV Move MVN Move Not
ADD Add ADC Add with Carry
SUB Subtract SBC Subtract with Carry
RSB Reverse Subtract RSC Reverse Subtract with Carry
CMP Compare CMN Compare Negated
TST Test TEQ Test Equivalence
AND Logical AND BIC Bit Clear
EOR Logical Exclusive OR ORR Logical (inclusive) OR
MUL Multiply MLA Multiply Accumulate
SMULL Sign Long Multiply UMULL Unsigned Long Multiply
SMLAL Signed Long Multiply Accumulate UMLAL
Unsigned Long Multiply
Accumulate
MSR Move to Status Register MRS Move From Status Register
B Branch BL Branch and Link
BX Branch and Exchange SWI Software Interrupt
LDR Load Word STR Store Word
LDRSH Load Signed Halfword
LDRSB Load Signed Byte
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRBT
Load Register Byte with
Translation
STRBT
Store Register Byte with
Translation
LDRT Load Register with Translation STRT Store Register with Translation
LDM Load Multiple STM Store Multiple
SWP Swap Word SWPB Swap Byte
MCR Move To Coprocessor MRC Move From Coprocessor
LDC Load To Coprocessor STC Store From Coprocessor
CDP Coprocessor Data Processing