Datasheet

364
SAM9M10 [DATASHEET]
6355FATARM12-Mar-13
27.5 Signal Description
27.6 Product Dependencies
27.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the SPI pins to their peripheral functions.
27.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first config-
ure the PMC to enable the SPI clock.
Table 27-1. Signal Description
Pin Name Pin Description
Type
Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Slave In Output Input
SPCK Serial Clock Output Input
NPCS1-NPCS3 Peripheral Chip Selects Output Unused
NPCS0/NSS Peripheral Chip Select/Slave Select Output Input
Table 27-2. I/O Lines
Instance Signal I/O Line Peripheral
SPI0 SPI0_MISO PB0 A
SPI0 SPI0_MOSI PB1 A
SPI0 SPI0_NPCS0 PB3 A
SPI0 SPI0_NPCS1 PB18 B
SPI0 SPI0_NPCS1 PD24 A
SPI0 SPI0_NPCS2 PB19 B
SPI0 SPI0_NPCS2 PD25 A
SPI0 SPI0_NPCS3 PD27 B
SPI0 SPI0_SPCK PB2 A
SPI1 SPI1_MISO PB14 A
SPI1 SPI1_MOSI PB15 A
SPI1 SPI1_NPCS0 PB17 A
SPI1 SPI1_NPCS1 PD28 B
SPI1 SPI1_NPCS2 PD18 A
SPI1 SPI1_NPCS3 PD19 A
SPI1 SPI1_SPCK PB16 A