Datasheet

354
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
• MDIV: Master Clock Division
Note: It is forbidden to modify MDIV and CSS at the same access. Each field must be modified separately with a wait for MCKRDY flag
between the first field modification and the second field modification.
• PLLADIV2: PLLA divisor by 2
MDIV Master Clock Division
00
Master Clock is Prescaler Output Clock divided by 1.
Warning: SysClk DDR and DDRCK are not available.
01
Master Clock is Prescaler Output Clock divided by 2.
SysClk DDR is equal to 2 x MCK.
DDRCK is equal to MCK.
10
Master Clock is Prescaler Output Clock divided by 4.
SysClk DDR is equal to 2 x MCK.
DDRCK is equal to MCK.
11
Master Clock is Prescaler Output Clock divided by 3.
SysClk DDR is equal to 2 x MCK.
DDRCK is equal to MCK.
PLLADIV2 PLLA Clock Division
0 PLLA clock frequency is divided by 1.
1 PLLA clock frequency is divided by 2.