Datasheet

247
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
22.5.6 Write Protected Registers
To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be write-
protected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Sta-
tus Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has
been attempted.
The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Register
(DDRSDRC_WPSR).
Following is a list of the write protected registers:
• “DDRSDRC Mode Register” on page 252
• “DDRSDRC Refresh Timer Register” on page 253
• “DDRSDRC Configuration Register” on page 254
• “DDRSDRC Timing Parameter 0 Register” on page 257
• “DDRSDRC Timing Parameter 1 Register” on page 259
• “DDRSDRC Timing Parameter 2 Register” on page 260
• “DDRSDRC Memory Device Register” on page 263
• “DDRSDRC High Speed Register” on page 265