Datasheet

246
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
1. Idle cycles: When no master is connected to the SDRAM device.
2. Single cycles: When a slave is currently doing a single access.
3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For bursts of defined
length, predicted end of burst matches the size of the transfer. For bursts of undefined length, predicted
end of burst is generated at the end of each four beat boundary inside the INCR transfer.
4. Anticipated Access: When an anticipate read access is done while current access is not complete, the
arbitration scheme can be changed if the anticipated access is not the next access serviced by the arbitra-
tion scheme.
Figure 22-25. Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1
NOP READ NOP
0
NOPPRECH ACT READ
1
1
2
Anticipate command, Precharge/Active Bank 2
Trp
Read access in Bank 1
SDClK
A[12:0]
COMMAND
BA[1:0]
DQS[1:0]
Da
Db
Dc
Dd De Df Dg Dh
Di Dj Dk Dl
D[15:0]
3
DM1:0]