Datasheet

243
SAM9M10 [DATASHEET]
6355FATARM12-Mar-13
The exit procedure is faster than in self refresh mode. See Figure 22-22 on page 243. The DDRSDRC returns to
power-down mode as soon as the SDRAM device is not selected. It is possible to define when power-down mode
is enabled by setting the register LPR, timeout command bit.
00 = Power-down mode is enabled as soon as the SDRAM device is not selected
01 = Power-down mode is enabled 64 clock cycles after completion of the last access
10 = Power-down mode is enabled 128 clock cycles after completion of the last access
Figure 22-22. Power-down Entry/Exit, Timeout = 0
22.5.4.3 Deep Power-down Mode
The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal
voltage generators inside the device are stopped and all data is lost.
This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is enabled, the
DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. To exit deep power-down mode, the
low-power bits (LPCB) must be set to “00”, an initialization sequence must be generated by software. See Section
22.4.2 “Low-power DDR1-SDRAM Initialization” on page 227.
Entry power down mode
Exit power down mode
SDCLK
A[12:0]
READ BST NOP READ
COMMAND
CKE
0
BA[1:0]
DQS[1:0]
Da Db
D[15:0]
3
DM[1:0]