Datasheet

236
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
For a definition of timing parameters, refer to Section 22.8.3 “DDRSDRC Configuration Register” on page 254.
Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maxi-
mum number of column locations that can be accessed for a given read command. When the read command is
issued, 8 columns are selected. All accesses for that burst take place within these eight columns, meaning that the
burst wraps within these 8 columns if the boundary is reached. These 8 columns are selected by addr[13:3];
addr[2:0] is used to select the starting location within the block.
In the case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of
the SDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but
since the burst length is programmed to 8, the next access is 0x00. Since the boundary is reached, the burst
wraps. The DDRSDRC takes into account this feature of the SDRAM device. In the case of DDR-SDRAM devices,
transfers start at address 0x04/0x08/0x0C. In the case of SDR-SDRAM devices, transfers start at address
0x14/0x18/0x1C. Two read commands are issued to avoid wrapping when the boundary is reached. The last read
command may generate additional reading (1 read cmd = 4 DDR words or 1 read cmd = 8 SDR words).
To avoid additional reading, it is possible to use the burst stop command to truncate the read burst and to decrease
power consumption.
Figure 22-11. Single Read Access, Row Close, Latency = 2,Low-power DDR1-SDRAM Device
Trp Trcd
Latency = 2
SDCLK
Row a Col a
A[12:0]
NOP PRCHG NOP ACT NOP READ BST NOP
COMMAND
0
BA[1:0]
DQS[1]
DQS[0]
Da Db
D[15:0]
3
DM[1:0]