Datasheet

18
SAM9M10 [DATASHEET]
6355FATARM12-Mar-13
DDR_D[15] <=> DELAY2[31:28]
DDR_A[13:0] controlled by 2 registers, DELAY3 and DELAY4, located in the DDRSDRC user interface
DDR_A[0] <=> DELAY3[3:0],
DDR_A[1] <=> DELAY3[7:4], ...,
DDR_A[6] <=> DELAY3[27:24],
DDR_A[7] <=> DELAY3[31:28]
DDR_A[8] <=> DELAY4[3:0],
DDR_A[9] <=> DELAY4[7:4], ...,
DDR_A[12] <=> DELAY4[19:16],
DDR_A[13] <=> DELAY4[23:20]
EBI (DDRSDRC\HSMC3\Nandflash)
D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the HSMC3 user interface
D[0] <=> DELAY1[3:0],
D[1] <=> DELAY1[7:4],...,
D[6] <=> DELAY1[27:24],
D[7] <=> DELAY1[31:28]
D[8] <=> DELAY2[3:0],
D[9] <=> DELAY2[7:4],...,
D[14] <=> DELAY2[27:24],
D[15] <=> DELAY2[31:28]
D[31,16]on PIOC[31:16] controlled by 2 registers, DELAY3 and DELAY4, located in the HSMC3 user interface
D[16] <=> DELAY3[3:0],
D[17] <=> DELAY3[7:4],...,
D[22] <=> DELAY3[27:24],
PC[23] <=> DELAY3[31:28]
D[24] <=> DELAY4[3:0],
D[25] <=> DELAY4[7:4],...,
D[30] <=> DELAY4[27:24],
D[31] <=> DELAY4[31:28]
A[25:0], controlled by 4 registers, DELAY5, DELAY6, DELAY7and DELAY8, located in the HSMC3 user interface
A[0] <=> DELAY5[3:0],
A[1] <=> DELAY5[7:4],...,
A[6] <=> DELAY5[27:24],
A[7] <=> DELAY5[31:28]
A[8] <=> DELAY6[3:0],
A[9] <=> DELAY6[7:4],...,
A[14] <=> DELAY6[27:24],
A[15] <=> DELAY6[31:28]
A[16] <=> DELAY7[3:0],