Datasheet
142
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
19.7.4 Bus Matrix Priority Registers B For Slaves
Name: MATRIX_PRBS0...MATRIX_PRBS7
Addresses: 0xFFFFEA84 [0], 0xFFFFEA8C [1], 0xFFFFEA94 [2], 0xFFFFEA9C [3], 0xFFFFEAA4 [4], 0xFFFFEAAC [5],
0xFFFFEAB4 [6], 0xFFFFEABC [7]
Access: Read-write
This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
All the masters programmed with the same MxPR value for the slave make up a priority pool.
Round-Robin arbitration is used inside the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used inside intermediate priority pools (MxPR = 1) and (MxPR = 2).
See Section 19.5.2 “Arbitration Priority Scheme” for details.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– M11PR M10PR
76543210
– – M9PR – – M8PR