Datasheet

iv
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
21.2 I/O Lines Description .........................................................................................185
21.3 Multiplexed Signals ............................................................................................185
21.4 Application Example ..........................................................................................186
21.5 Product Dependencies ......................................................................................186
21.6 External Memory Mapping .................................................................................187
21.7 Connection to External Devices ........................................................................187
21.8 Standard Read and Write Protocols ..................................................................192
21.9 Automatic Wait States .......................................................................................200
21.10 Data Float Wait States .....................................................................................205
21.11 External Wait ...................................................................................................209
21.12 Slow Clock Mode .............................................................................................215
21.13 Asynchronous Page Mode ..............................................................................218
21.14 Programmable IO Delays ................................................................................221
21.15 Static Memory Controller (SMC) User Interface ..............................................222
22 DDR/SDR SDRAM Controller (DDRSDRC) .........................................229
22.1 Description .........................................................................................................229
22.2 Embedded Characteristics ................................................................................229
22.3 DDRSDRC Module Diagram .............................................................................231
22.4 Initialization Sequence .......................................................................................232
22.5 Functional Description .......................................................................................237
22.6 Software Interface/SDRAM Organization, Address Mapping ............................256
22.7 Programmable IO Delays ..................................................................................258
22.8 DDR SDR SDRAM Controller (DDRSDRC) User Interface ...............................259
23 Error Corrected Code Controller (ECC) .............................................279
23.1 Description .........................................................................................................279
23.2 Block Diagram ...................................................................................................279
23.3 Functional Description .......................................................................................279
23.4 Error Corrected Code Controller (ECC) User Interface .....................................284
23.5 Registers for 1 ECC for a page of 512/1024/2048/4096 bytes ..........................295
23.6 Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes,
8-bit word ......................................................................................................297
23.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes,
8-bit word ......................................................................................................305
24 Peripheral DMA Controller (PDC) .......................................................321
24.1 Description .........................................................................................................321
24.2 Embedded Characteristics ................................................................................321