Datasheet
1328
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Notes: 1. For output signals, Min and Max access time must be extracted. The Min access time is the time between the SPCK rising or
falling edge and the signal change. The Max access time is the time between the SPCK rising or falling edge and the signal
stabilization. Figure 47-9 illustrates Min and Max accesses for SPI2. The same applies to SPI5, SPI6, SPI9.
SPI
9
SPCK rising to MISO 4.7
(1)
17.1
(1)
ns
SPI
10
MOSI Setup time before SPCK falls 0.4 ns
SPI
11
MOSI Hold time after SPCK falls 0 ns
SPI
12
NPCS0 setup to SPCK rising 10.3 ns
SPI
13
NPCS0 hold after SPCK falling 2.0 ns
SPI
14
NPCS0 setup to SPCK falling 10.7 ns
SPI
15
NPCS0 hold after SPCK rising 2.0 ns
SPI
16
NPCS0 falling to MISO valid 16.0 ns
Table 47-47. UART SPI Timings with 1.8V Peripheral Supply
Symbol Parameter Cond Min Max Units
Master Mode
SPI
0
SPCK Period ns
SPI
1
Input Data Setup Time 20.6 ns
SPI
2
Input Data Hold Time 0 ns
SPI
3
Chip Select Active to Serial Clock 6.0 ns
SPI
4
Output Data Setup Time 0.2 ns
SPI
5
Serial Clock to Chip Select Inactive 0 ns
Slave Mode
SPI
6
SPCK falling to MISO 4.4 20.7 ns
SPI
7
MOSI Setup time before SPCK rises 7.6 ns
SPI
8
MOSI Hold time after SPCK rises 3.1 ns
SPI
9
SPCK rising to MISO 5.6 20.6 ns
SPI
10
MOSI Setup time before SPCK falls 0.8 ns
SPI
11
MOSI Hold time after SPCK falls 0 ns
SPI
12
NPCS0 setup to SPCK rising 10.2 ns
SPI
13
NPCS0 hold after SPCK falling 1.9 ns
SPI
14
NPCS0 setup to SPCK falling 11.0 ns
SPI
15
NPCS0 hold after SPCK rising 2.2 ns
SPI
16
NPCS0 falling to MISO valid 18.9 ns
Table 47-46. UART SPI Timings with 3.3V Peripheral Supply (Continued)
Symbol Parameter Cond Min Max Units