Datasheet

1318
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 47-10. Min and Max Access Time for SPI Output Signal
47.15.2 SSC
47.15.2.1 Timing Conditions
Timings are given assuming a capacitance load on Table 47-35.
SPI
9
SPCK rising to MISO 5.5 18.7 ns
SPI
10
MOSI Setup time before SPCK falls 0.5 ns
SPI
11
MOSI Hold time after SPCK falls 1.4 ns
SPI
12
NPCS0 setup to SPCK rising 17.4 ns
SPI
13
NPCS0 hold after SPCK falling 15.5 ns
SPI
14
NPCS0 setup to SPCK falling 17.8 ns
SPI
15
NPCS0 hold after SPCK rising 15.3 ns
SPI
16
NPCS0 falling to MISO valid 5.4 17.7 ns
Table 47-34. SPI Timings with 1.8V Peripheral Supply (Continued)
Symbol Parameter Cond Min Max Units
SPCK
MISO
MOSI
SPI
2max
SPI
0
SPI
1
SPI
2min
Table 47-35. Capacitance Load
Corner
Supply MAX MIN
3.3V 30pF 0 pF
1.8V 20pF 0 pF